From 934d2c8f7f51d6e148e2b034e88a5eb6e1b9c98a Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Sun, 13 Jun 2021 09:39:23 -0700 Subject: [PATCH] i915g: Handle fragment depth being in OUT[1] not OUT[0]. Prevents regressions when switching to nir-to-tgsi which orders the outputs differently. Reviewed-by: Adam Jackson Part-of: --- src/gallium/drivers/i915/i915_fpc_translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c b/src/gallium/drivers/i915/i915_fpc_translate.c index cbcaeea..46ddff5 100644 --- a/src/gallium/drivers/i915/i915_fpc_translate.c +++ b/src/gallium/drivers/i915/i915_fpc_translate.c @@ -1186,8 +1186,10 @@ i915_fini_compile(struct i915_context *i915, struct i915_fp_compile *p) static void i915_fixup_depth_write(struct i915_fp_compile *p) { - /* XXX assuming pos/depth is always in output[0] */ - if (p->shader->info.num_outputs != 0 && p->shader->info.output_semantic_name[0] == TGSI_SEMANTIC_POSITION) { + for (int i = 0; i < p->shader->info.num_outputs; i++) { + if (p->shader->info.output_semantic_name[i] != TGSI_SEMANTIC_POSITION) + continue; + const uint depth = UREG(REG_TYPE_OD, 0); i915_emit_arith(p, -- 2.7.4