From 934be5fecf3c51f3219b4df79762333b1e3e0623 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 19 Sep 2018 00:23:37 +0000 Subject: [PATCH] AArch64MacroFusion: Factor out some opcode handling code; NFC llvm-svn: 342521 --- llvm/lib/Target/AArch64/AArch64MacroFusion.cpp | 231 ++++++++++++------------- 1 file changed, 110 insertions(+), 121 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp index bc0168e..9ec0ad3 100644 --- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp +++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp @@ -20,102 +20,93 @@ using namespace llvm; namespace { -// Fuse CMN, CMP, TST followed by Bcc. -static bool isArithmeticBccPair(const MachineInstr *FirstMI, - const MachineInstr &SecondMI) { - if (SecondMI.getOpcode() == AArch64::Bcc) { - // Assume the 1st instr to be a wildcard if it is unspecified. - if (!FirstMI) - return true; +/// CMN, CMP, TST followed by Bcc +static bool isArithmeticBccPair(unsigned FirstOpcode, unsigned SecondOpcode, + const MachineInstr *FirstMI) { + if (SecondOpcode != AArch64::Bcc) + return false; - switch (FirstMI->getOpcode()) { - case AArch64::ADDSWri: - case AArch64::ADDSWrr: - case AArch64::ADDSXri: - case AArch64::ADDSXrr: - case AArch64::ANDSWri: - case AArch64::ANDSWrr: - case AArch64::ANDSXri: - case AArch64::ANDSXrr: - case AArch64::SUBSWri: - case AArch64::SUBSWrr: - case AArch64::SUBSXri: - case AArch64::SUBSXrr: - case AArch64::BICSWrr: - case AArch64::BICSXrr: - return true; - case AArch64::ADDSWrs: - case AArch64::ADDSXrs: - case AArch64::ANDSWrs: - case AArch64::ANDSXrs: - case AArch64::SUBSWrs: - case AArch64::SUBSXrs: - case AArch64::BICSWrs: - case AArch64::BICSXrs: - // Shift value can be 0 making these behave like the "rr" variant... - return (!AArch64InstrInfo::hasShiftedReg(*FirstMI)); - } + switch (FirstOpcode) { + case AArch64::INSTRUCTION_LIST_END: + return true; + case AArch64::ADDSWri: + case AArch64::ADDSWrr: + case AArch64::ADDSXri: + case AArch64::ADDSXrr: + case AArch64::ANDSWri: + case AArch64::ANDSWrr: + case AArch64::ANDSXri: + case AArch64::ANDSXrr: + case AArch64::SUBSWri: + case AArch64::SUBSWrr: + case AArch64::SUBSXri: + case AArch64::SUBSXrr: + case AArch64::BICSWrr: + case AArch64::BICSXrr: + return true; + case AArch64::ADDSWrs: + case AArch64::ADDSXrs: + case AArch64::ANDSWrs: + case AArch64::ANDSXrs: + case AArch64::SUBSWrs: + case AArch64::SUBSXrs: + case AArch64::BICSWrs: + case AArch64::BICSXrs: + // Shift value can be 0 making these behave like the "rr" variant... + return !AArch64InstrInfo::hasShiftedReg(*FirstMI); } return false; } -// Fuse ALU operations followed by CBZ/CBNZ. -static bool isArithmeticCbzPair(const MachineInstr *FirstMI, - const MachineInstr &SecondMI) { - unsigned SecondOpcode = SecondMI.getOpcode(); +/// ALU operations followed by CBZ/CBNZ. +static bool isArithmeticCbzPair(unsigned FirstOpcode, unsigned SecondOpcode, + const MachineInstr *FirstMI) { + if (SecondOpcode != AArch64::CBNZW && + SecondOpcode != AArch64::CBNZX && + SecondOpcode != AArch64::CBZW && + SecondOpcode != AArch64::CBZX) + return false; - if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX || - SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) { - // Assume the 1st instr to be a wildcard if it is unspecified. - if (!FirstMI) - return true; - - switch (FirstMI->getOpcode()) { - case AArch64::ADDWri: - case AArch64::ADDWrr: - case AArch64::ADDXri: - case AArch64::ADDXrr: - case AArch64::ANDWri: - case AArch64::ANDWrr: - case AArch64::ANDXri: - case AArch64::ANDXrr: - case AArch64::EORWri: - case AArch64::EORWrr: - case AArch64::EORXri: - case AArch64::EORXrr: - case AArch64::ORRWri: - case AArch64::ORRWrr: - case AArch64::ORRXri: - case AArch64::ORRXrr: - case AArch64::SUBWri: - case AArch64::SUBWrr: - case AArch64::SUBXri: - case AArch64::SUBXrr: - return true; - case AArch64::ADDWrs: - case AArch64::ADDXrs: - case AArch64::ANDWrs: - case AArch64::ANDXrs: - case AArch64::SUBWrs: - case AArch64::SUBXrs: - case AArch64::BICWrs: - case AArch64::BICXrs: - // Shift value can be 0 making these behave like the "rr" variant... - return (!AArch64InstrInfo::hasShiftedReg(*FirstMI)); - } + switch (FirstOpcode) { + case AArch64::INSTRUCTION_LIST_END: + return true; + case AArch64::ADDWri: + case AArch64::ADDWrr: + case AArch64::ADDXri: + case AArch64::ADDXrr: + case AArch64::ANDWri: + case AArch64::ANDWrr: + case AArch64::ANDXri: + case AArch64::ANDXrr: + case AArch64::EORWri: + case AArch64::EORWrr: + case AArch64::EORXri: + case AArch64::EORXrr: + case AArch64::ORRWri: + case AArch64::ORRWrr: + case AArch64::ORRXri: + case AArch64::ORRXrr: + case AArch64::SUBWri: + case AArch64::SUBWrr: + case AArch64::SUBXri: + case AArch64::SUBXrr: + return true; + case AArch64::ADDWrs: + case AArch64::ADDXrs: + case AArch64::ANDWrs: + case AArch64::ANDXrs: + case AArch64::SUBWrs: + case AArch64::SUBXrs: + case AArch64::BICWrs: + case AArch64::BICXrs: + // Shift value can be 0 making these behave like the "rr" variant... + return !AArch64InstrInfo::hasShiftedReg(*FirstMI); } return false; } -// Fuse AES crypto encoding or decoding. -static bool isAESPair(const MachineInstr *FirstMI, - const MachineInstr &SecondMI) { - // Assume the 1st instr to be a wildcard if it is unspecified. - unsigned FirstOpcode = - FirstMI ? FirstMI->getOpcode() - : static_cast(AArch64::INSTRUCTION_LIST_END); - unsigned SecondOpcode = SecondMI.getOpcode(); - +/// AES crypto encoding or decoding. +static bool isAESPair(unsigned FirstOpcode, unsigned SecondOpcode) { // AES encode. if ((FirstOpcode == AArch64::INSTRUCTION_LIST_END || FirstOpcode == AArch64::AESErr) && @@ -132,15 +123,10 @@ static bool isAESPair(const MachineInstr *FirstMI, return false; } -// Fuse literal generation. -static bool isLiteralsPair(const MachineInstr *FirstMI, +/// Literal generation. +static bool isLiteralsPair(unsigned FirstOpcode, unsigned SecondOpcode, + const MachineInstr *FirstMI, const MachineInstr &SecondMI) { - // Assume the 1st instr to be a wildcard if it is unspecified. - unsigned FirstOpcode = - FirstMI ? FirstMI->getOpcode() - : static_cast(AArch64::INSTRUCTION_LIST_END); - unsigned SecondOpcode = SecondMI.getOpcode(); - // PC relative address. if ((FirstOpcode == AArch64::INSTRUCTION_LIST_END || FirstOpcode == AArch64::ADRP) && @@ -170,10 +156,8 @@ static bool isLiteralsPair(const MachineInstr *FirstMI, } // Fuse address generation and loads or stores. -static bool isAddressLdStPair(const MachineInstr *FirstMI, +static bool isAddressLdStPair(unsigned FirstOpcode, unsigned SecondOpcode, const MachineInstr &SecondMI) { - unsigned SecondOpcode = SecondMI.getOpcode(); - switch (SecondOpcode) { case AArch64::STRBBui: case AArch64::STRBui: @@ -198,13 +182,11 @@ static bool isAddressLdStPair(const MachineInstr *FirstMI, case AArch64::LDRSHWui: case AArch64::LDRSHXui: case AArch64::LDRSWui: - // Assume the 1st instr to be a wildcard if it is unspecified. - if (!FirstMI) + switch (FirstOpcode) { + case AArch64::INSTRUCTION_LIST_END: return true; - - switch (FirstMI->getOpcode()) { case AArch64::ADR: - return (SecondMI.getOperand(2).getImm() == 0); + return SecondMI.getOperand(2).getImm() == 0; case AArch64::ADRP: return true; } @@ -212,23 +194,21 @@ static bool isAddressLdStPair(const MachineInstr *FirstMI, return false; } -// Fuse compare and conditional select. -static bool isCCSelectPair(const MachineInstr *FirstMI, - const MachineInstr &SecondMI) { - unsigned SecondOpcode = SecondMI.getOpcode(); - +// Compare and conditional select. +static bool isCCSelectPair(unsigned FirstOpcode, unsigned SecondOpcode, + const MachineInstr *FirstMI) { // 32 bits if (SecondOpcode == AArch64::CSELWr) { // Assume the 1st instr to be a wildcard if it is unspecified. - if (!FirstMI) + if (FirstOpcode == AArch64::INSTRUCTION_LIST_END) return true; if (FirstMI->definesRegister(AArch64::WZR)) - switch (FirstMI->getOpcode()) { + switch (FirstOpcode) { case AArch64::SUBSWrs: - return (!AArch64InstrInfo::hasShiftedReg(*FirstMI)); + return !AArch64InstrInfo::hasShiftedReg(*FirstMI); case AArch64::SUBSWrx: - return (!AArch64InstrInfo::hasExtendedReg(*FirstMI)); + return !AArch64InstrInfo::hasExtendedReg(*FirstMI); case AArch64::SUBSWrr: case AArch64::SUBSWri: return true; @@ -237,16 +217,16 @@ static bool isCCSelectPair(const MachineInstr *FirstMI, // 64 bits else if (SecondOpcode == AArch64::CSELXr) { // Assume the 1st instr to be a wildcard if it is unspecified. - if (!FirstMI) + if (FirstOpcode == AArch64::INSTRUCTION_LIST_END) return true; if (FirstMI->definesRegister(AArch64::XZR)) - switch (FirstMI->getOpcode()) { + switch (FirstOpcode) { case AArch64::SUBSXrs: - return (!AArch64InstrInfo::hasShiftedReg(*FirstMI)); + return !AArch64InstrInfo::hasShiftedReg(*FirstMI); case AArch64::SUBSXrx: case AArch64::SUBSXrx64: - return (!AArch64InstrInfo::hasExtendedReg(*FirstMI)); + return !AArch64InstrInfo::hasExtendedReg(*FirstMI); case AArch64::SUBSXrr: case AArch64::SUBSXri: return true; @@ -264,17 +244,26 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, const MachineInstr &SecondMI) { const AArch64Subtarget &ST = static_cast(TSI); - if (ST.hasArithmeticBccFusion() && isArithmeticBccPair(FirstMI, SecondMI)) + // Assume the 1st instr to be a wildcard if it is unspecified. + unsigned FirstOpc = + FirstMI ? FirstMI->getOpcode() + : static_cast(AArch64::INSTRUCTION_LIST_END); + unsigned SecondOpc = SecondMI.getOpcode(); + + if (ST.hasArithmeticBccFusion() && + isArithmeticBccPair(FirstOpc, SecondOpc, FirstMI)) return true; - if (ST.hasArithmeticCbzFusion() && isArithmeticCbzPair(FirstMI, SecondMI)) + if (ST.hasArithmeticCbzFusion() && + isArithmeticCbzPair(FirstOpc, SecondOpc, FirstMI)) return true; - if (ST.hasFuseAES() && isAESPair(FirstMI, SecondMI)) + if (ST.hasFuseAES() && isAESPair(FirstOpc, SecondOpc)) return true; - if (ST.hasFuseLiterals() && isLiteralsPair(FirstMI, SecondMI)) + if (ST.hasFuseLiterals() && + isLiteralsPair(FirstOpc, SecondOpc, FirstMI, SecondMI)) return true; - if (ST.hasFuseAddress() && isAddressLdStPair(FirstMI, SecondMI)) + if (ST.hasFuseAddress() && isAddressLdStPair(FirstOpc, SecondOpc, SecondMI)) return true; - if (ST.hasFuseCCSelect() && isCCSelectPair(FirstMI, SecondMI)) + if (ST.hasFuseCCSelect() && isCCSelectPair(FirstOpc, SecondOpc, FirstMI)) return true; return false; -- 2.7.4