From 9335bf0ec5c19bbaf027847682c44451b6affef8 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Fri, 19 Aug 2016 16:35:05 +0000 Subject: [PATCH] [Hexagon] Fix incorrect generation of S4_subi_asl_ri Patch by Jyotsna Verma. llvm-svn: 279267 --- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 43 ++++++++++------ llvm/test/CodeGen/Hexagon/subi-asl.ll | 70 +++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 14 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/subi-asl.ll diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 27d4ad3..263e55a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2681,13 +2681,11 @@ def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>; // Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5)) let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, hasNewValue = 1, opNewValue = 0 in -class T_S4_ShiftOperate MajOp, InstrItinClass Itin> +class T_S4_ShiftOperate MajOp, InstrItinClass Itin> : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5), "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))", - [(set (i32 IntRegs:$Rd), - (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))], - "$Rd = $Rx", Itin> { + [], "$Rd = $Rx", Itin> { bits<5> Rd; bits<8> u8; @@ -2706,21 +2704,38 @@ class T_S4_ShiftOperate MajOp, - InstrItinClass Itin> { - def _asl_ri : T_S4_ShiftOperate; - def _lsr_ri : T_S4_ShiftOperate; +multiclass T_ShiftOperate MajOp, InstrItinClass Itin> { + def _asl_ri : T_S4_ShiftOperate; + def _lsr_ri : T_S4_ShiftOperate; } +defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>; +defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>; +defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>; +defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>; + +class T_Shift_CommOp_pat + : Pat<(Op (ShOp IntRegs:$Rx, u5ImmPred:$U5), u32ImmPred:$u8), + (MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>; + let AddedComplexity = 200 in { - defm S4_addi : T_ShiftOperate<"add", add, 0b10, ALU64_tc_2_SLOT23>; - defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>; + def : T_Shift_CommOp_pat ; + def : T_Shift_CommOp_pat ; + def : T_Shift_CommOp_pat ; + def : T_Shift_CommOp_pat ; +} + +let AddedComplexity = 30 in { + def : T_Shift_CommOp_pat ; + def : T_Shift_CommOp_pat ; } -let AddedComplexity = 30 in -defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>; +class T_Shift_Op_pat + : Pat<(Op u32ImmPred:$u8, (ShOp IntRegs:$Rx, u5ImmPred:$U5)), + (MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>; -defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>; +def : T_Shift_Op_pat ; +def : T_Shift_Op_pat ; let AddedComplexity = 200 in { def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)), diff --git a/llvm/test/CodeGen/Hexagon/subi-asl.ll b/llvm/test/CodeGen/Hexagon/subi-asl.ll new file mode 100644 index 0000000..f0b27e8 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/subi-asl.ll @@ -0,0 +1,70 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check if S4_subi_asl_ri is being generated correctly. + +; CHECK-LABEL: yes_sub_asl +; CHECK: [[REG1:(r[0-9]+)]] = sub(#0, asl([[REG1]], #1)) + +; CHECK-LABEL: no_sub_asl +; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}}, #1) +; CHECK: r{{[0-9]+}} = sub([[REG2]], r{{[0-9]+}}) + +%struct.rtx_def = type { i16, i8 } + +@this_insn_number = external global i32, align 4 + +; Function Attrs: nounwind +define void @yes_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 { +entry: + %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0 + %0 = load i16, i16* %code, align 4 + switch i16 %0, label %return [ + i16 2, label %if.end + i16 5, label %if.end + ] + +if.end: + %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0 + %1 = load i16, i16* %code6, align 4 + %cmp8 = icmp eq i16 %1, 56 + %conv9 = zext i1 %cmp8 to i32 + %2 = load i32, i32* @this_insn_number, align 4 + %3 = mul i32 %2, -2 + %sub = add nsw i32 %conv9, %3 + tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2 + br label %return + +return: + ret void +} + +declare void @reg_is_born(%struct.rtx_def*, i32) #1 + +; Function Attrs: nounwind +define void @no_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 { +entry: + %code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0 + %0 = load i16, i16* %code, align 4 + switch i16 %0, label %return [ + i16 2, label %if.end + i16 5, label %if.end + ] + +if.end: + %1 = load i32, i32* @this_insn_number, align 4 + %mul = mul nsw i32 %1, 2 + %code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0 + %2 = load i16, i16* %code6, align 4 + %cmp8 = icmp eq i16 %2, 56 + %conv9 = zext i1 %cmp8 to i32 + %sub = sub nsw i32 %mul, %conv9 + tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2 + br label %return + +return: + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv5" } +attributes #1 = { "target-cpu"="hexagonv5" } +attributes #2 = { nounwind } -- 2.7.4