From 9327780da68bf2bca8533c00bbd2ff1e91f32879 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 26 Jan 2017 02:16:18 +0100 Subject: [PATCH] winsys/amdgpu: fix ADDR_REGISTER_VALUE::backendDisables MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This would be a fix if the value was used anywhere. Reviewed-by: Nicolai Hähnle --- src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 08989b5..abe2b2a 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -111,7 +111,7 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws) regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg; regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2; - regValue.backendDisables = ws->amdinfo.backend_disable[0]; + regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask; regValue.pTileConfig = ws->amdinfo.gb_tile_mode; regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode); if (ws->info.chip_class == SI) { -- 2.7.4