From 929932954d0f481e7e6602001ed7a3f0151774aa Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Wed, 27 Mar 2019 23:12:19 +0000
Subject: [PATCH] [X86] Add test cases from PR27202.

llvm-svn: 357132
---
 llvm/test/CodeGen/X86/pr27202.ll | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/pr27202.ll

diff --git a/llvm/test/CodeGen/X86/pr27202.ll b/llvm/test/CodeGen/X86/pr27202.ll
new file mode 100644
index 0000000..e0483e9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr27202.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i1 @foo(i32 %i) optsize {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andl $305419896, %edi # imm = 0x12345678
+; CHECK-NEXT:    movl $305419896, %eax # imm = 0x12345678
+; CHECK-NEXT:    cmpl %eax, %edi
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retq
+  %and = and i32 %i, 305419896
+  %cmp = icmp eq i32 %and, 305419896
+  ret i1 %cmp
+}
+
+define zeroext i1 @g(i32 %x) optsize {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orl $1, %edi
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    cmpl %eax, %edi
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retq
+  %t0 = or i32 %x, 1
+  %t1 = icmp eq i32 %t0, 1
+  ret i1 %t1
+}
-- 
2.7.4