From 92417ebbd10382436136ed5e755be567304ac139 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 23 Mar 2021 12:51:55 -0400
Subject: [PATCH] [InstCombine] add tests for sub of umin; NFC

Potential missing fold noted in D98152
---
 llvm/test/Transforms/InstCombine/sub-minmax.ll | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/llvm/test/Transforms/InstCombine/sub-minmax.ll b/llvm/test/Transforms/InstCombine/sub-minmax.ll
index 63a884a..83b2109 100644
--- a/llvm/test/Transforms/InstCombine/sub-minmax.ll
+++ b/llvm/test/Transforms/InstCombine/sub-minmax.ll
@@ -1,6 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+declare i5 @llvm.umin.i5(i5, i5)
+declare <2 x i8> @llvm.umin.v2i8(<2 x i8>, <2 x i8>)
+
 define i32 @max_na_b_minux_na(i32 %A, i32 %B) {
 ; CHECK-LABEL: @max_na_b_minux_na(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
@@ -28,6 +31,52 @@ define i32 @na_minus_max_na_b(i32 %A, i32 %B) {
   ret i32 %x
 }
 
+define i5 @sub_umin(i5 %a, i5 %b) {
+; CHECK-LABEL: @sub_umin(
+; CHECK-NEXT:    [[UMIN:%.*]] = call i5 @llvm.umin.i5(i5 [[A:%.*]], i5 [[B:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = sub i5 [[A]], [[UMIN]]
+; CHECK-NEXT:    ret i5 [[R]]
+;
+  %umin = call i5 @llvm.umin.i5(i5 %a, i5 %b)
+  %r = sub i5 %a, %umin
+  ret i5 %r
+}
+
+define <2 x i8> @sub_umin_commute_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @sub_umin_commute_vec(
+; CHECK-NEXT:    [[UMIN:%.*]] = call <2 x i8> @llvm.umin.v2i8(<2 x i8> [[B:%.*]], <2 x i8> [[A:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = sub <2 x i8> [[B]], [[UMIN]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
+;
+  %umin = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %b, <2 x i8> %a)
+  %r = sub <2 x i8> %b, %umin
+  ret <2 x i8> %r
+}
+
+define i5 @sub_umin_uses(i5 %a, i5 %b, i5* %p) {
+; CHECK-LABEL: @sub_umin_uses(
+; CHECK-NEXT:    [[UMIN:%.*]] = call i5 @llvm.umin.i5(i5 [[A:%.*]], i5 [[B:%.*]])
+; CHECK-NEXT:    store i5 [[UMIN]], i5* [[P:%.*]], align 1
+; CHECK-NEXT:    [[R:%.*]] = sub i5 [[A]], [[UMIN]]
+; CHECK-NEXT:    ret i5 [[R]]
+;
+  %umin = call i5 @llvm.umin.i5(i5 %a, i5 %b)
+  store i5 %umin, i5* %p
+  %r = sub i5 %a, %umin
+  ret i5 %r
+}
+
+define i5 @sub_umin_no_common_op(i5 %a, i5 %b, i5 %c) {
+; CHECK-LABEL: @sub_umin_no_common_op(
+; CHECK-NEXT:    [[UMIN:%.*]] = call i5 @llvm.umin.i5(i5 [[A:%.*]], i5 [[B:%.*]])
+; CHECK-NEXT:    [[R:%.*]] = sub i5 [[C:%.*]], [[UMIN]]
+; CHECK-NEXT:    ret i5 [[R]]
+;
+  %umin = call i5 @llvm.umin.i5(i5 %a, i5 %b)
+  %r = sub i5 %c, %umin
+  ret i5 %r
+}
+
 define i32 @max_b_na_minus_na(i32 %A, i32 %B) {
 ; CHECK-LABEL: @max_b_na_minus_na(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
-- 
2.7.4