From 92205bf122b14e4beaaade612b6681dd21a926ab Mon Sep 17 00:00:00 2001 From: David Green Date: Sat, 24 Oct 2020 17:22:49 +0100 Subject: [PATCH] [ARM] Remove some dead code. NFC --- llvm/lib/Target/ARM/ARMInstrInfo.td | 9 --------- 1 file changed, 9 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index a1dce3d..c37734b 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -104,11 +104,6 @@ def SDT_ARMIntShiftParts : SDTypeProfile<2, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<4>]>; -// TODO Add another operand for 'Size' so that we can re-use this node when we -// start supporting *TP versions. -def SDT_ARMLoLoop : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, - SDTCisVT<1, OtherVT>]>; - def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; @@ -303,10 +298,6 @@ def SDTARMVCMPZ : SDTypeProfile<1, 2, [SDTCisInt<2>]>; def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>; def ARMvcmpz : SDNode<"ARMISD::VCMPZ", SDTARMVCMPZ>; -def ARMWLS : SDNode<"ARMISD::WLS", SDT_ARMLoLoop, [SDNPHasChain]>; -def ARMLE : SDNode<"ARMISD::LE", SDT_ARMLoLoop, [SDNPHasChain]>; -def ARMLoopDec : SDNode<"ARMISD::LOOP_DEC", SDTIntBinOp, [SDNPHasChain]>; - // 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a // vector register as a different vector type, without changing the contents of // the register. It differs from 'bitconvert' in that bitconvert reinterprets -- 2.7.4