From 9211da4215b6d48c8b9186b78274946789c559e9 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 20 Nov 2020 12:08:16 -0800 Subject: [PATCH] [RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode lists in RISCVRegisterInfo.td Addresses post-commit feedback from 77e25b5bc8860e23395f617dcca4940489f6355c --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 32 +++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index b4561af..cda75c8 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -97,8 +97,8 @@ let RegAltNameIndices = [ABIRegAltName] in { } } -def XLenVT : ValueTypeByHwMode<[RV64, RV32], - [i64, i32]>; +def XLenVT : ValueTypeByHwMode<[RV32, RV64], + [i32, i64]>; // The order of registers represents the preferred allocation sequence. // Registers are listed in the order caller-save, callee-save, specials. @@ -111,14 +111,14 @@ def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 0, 4) )> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // The order of registers represents the preferred allocation sequence. @@ -132,8 +132,8 @@ def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 1, 4) )> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add @@ -145,8 +145,8 @@ def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X3, X4 )> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add @@ -154,8 +154,8 @@ def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 8, 9) )> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // For indirect tail calls, we can't use callee-saved registers, as they are @@ -167,14 +167,14 @@ def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 28, 31) )> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { let RegInfos = RegInfoByHwMode< - [RV64, RV32], - [RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // Floating point registers -- 2.7.4