From 91ba65f2f0cacac286907b8a465f42b4e56aeda3 Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Wed, 3 Oct 2012 21:39:18 +0000 Subject: [PATCH] re PR target/51244 ([SH] Inefficient conditional branch and code around T bit) PR target/51244 * config/sh/sh.md (*mov_t_msb_neg): New insn and two accompanying unnamed split patterns. PR target/51244 * gcc.target/sh/pr51244-12.c: New. From-SVN: r192052 --- gcc/ChangeLog | 6 +++ gcc/config/sh/sh.md | 45 +++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.target/sh/pr51244-12.c | 68 ++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 gcc/testsuite/gcc.target/sh/pr51244-12.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fcdeec9..0ac802f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2012-10-03 Oleg Endo + PR target/51244 + * config/sh/sh.md (*mov_t_msb_neg): New insn and two accompanying + unnamed split patterns. + +2012-10-03 Oleg Endo + PR target/50457 * config/sh/sh.c (parse_validate_atomic_model_option): Handle name strings in sh_atomic_model. diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 8f0443a..91a09c5 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -10769,6 +10769,51 @@ label: (set (reg:SI T_REG) (const_int 1)) (use (match_dup 2))])]) +;; Use negc to store the T bit in a MSB of a reg in the following way: +;; T = 1: 0x80000000 -> reg +;; T = 0: 0x7FFFFFFF -> reg +;; This works because 0 - 0x80000000 = 0x80000000. +(define_insn_and_split "*mov_t_msb_neg" + [(set (match_operand:SI 0 "arith_reg_dest") + (minus:SI (const_int -2147483648) ;; 0x80000000 + (match_operand 1 "t_reg_operand"))) + (clobber (reg:SI T_REG))] + "TARGET_SH1" + "#" + "&& can_create_pseudo_p ()" + [(set (match_dup 2) (const_int -2147483648)) + (parallel [(set (match_dup 0) (minus:SI (neg:SI (match_dup 2)) + (reg:SI T_REG))) + (clobber (reg:SI T_REG))])] +{ + operands[2] = gen_reg_rtx (SImode); +}) + +;; These are essentially the same as above, but with the inverted T bit. +;; Combine recognizes the split patterns, but does not take them sometimes +;; if the T_REG clobber is specified. Instead it tries to split out the +;; T bit negation. Since these splits are supposed to be taken only by +;; combine, it will see the T_REG clobber of the *mov_t_msb_neg insn, so this +;; should be fine. +(define_split + [(set (match_operand:SI 0 "arith_reg_dest") + (plus:SI (match_operand 1 "negt_reg_operand") + (const_int 2147483647)))] ;; 0x7fffffff + "TARGET_SH1 && can_create_pseudo_p ()" + [(parallel [(set (match_dup 0) + (minus:SI (const_int -2147483648) (reg:SI T_REG))) + (clobber (reg:SI T_REG))])]) + +(define_split + [(set (match_operand:SI 0 "arith_reg_dest") + (if_then_else:SI (match_operand 1 "t_reg_operand") + (const_int 2147483647) ;; 0x7fffffff + (const_int -2147483648)))] ;; 0x80000000 + "TARGET_SH1 && can_create_pseudo_p ()" + [(parallel [(set (match_dup 0) + (minus:SI (const_int -2147483648) (reg:SI T_REG))) + (clobber (reg:SI T_REG))])]) + ;; The *negnegt pattern helps the combine pass to figure out how to fold ;; an explicit double T bit negation. (define_insn_and_split "*negnegt" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0222698..aa4ef67 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-10-03 Oleg Endo + + PR target/51244 + * gcc.target/sh/pr51244-12.c: New. + 2012-10-03 Dehao Chen PR middle-end/54782 diff --git a/gcc/testsuite/gcc.target/sh/pr51244-12.c b/gcc/testsuite/gcc.target/sh/pr51244-12.c new file mode 100644 index 0000000..ca8e2d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr51244-12.c @@ -0,0 +1,68 @@ +/* Check that the negc instruction is generated as expected for the cases + below. If we see a movrt or #-1 negc sequence it means that the pattern + which handles the inverted case does not work properly. */ +/* { dg-do compile { target "sh*-*-*" } } */ +/* { dg-options "-O1" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */ +/* { dg-final { scan-assembler-times "negc" 10 } } */ +/* { dg-final { scan-assembler-not "movrt|#-1|add|sub" } } */ + +int +test00 (int a, int b, int* x) +{ + return (a == b) ? 0x7FFFFFFF : 0x80000000; +} + +int +test00_inv (int a, int b) +{ + return (a != b) ? 0x80000000 : 0x7FFFFFFF; +} + +int +test01 (int a, int b) +{ + return (a >= b) ? 0x7FFFFFFF : 0x80000000; +} + +int +test01_inv (int a, int b) +{ + return (a < b) ? 0x80000000 : 0x7FFFFFFF; +} + +int +test02 (int a, int b) +{ + return (a > b) ? 0x7FFFFFFF : 0x80000000; +} + +int +test02_inv (int a, int b) +{ + return (a <= b) ? 0x80000000 : 0x7FFFFFFF; +} + +int +test03 (int a, int b) +{ + return ((a & b) == 0) ? 0x7FFFFFFF : 0x80000000; +} + +int +test03_inv (int a, int b) +{ + return ((a & b) != 0) ? 0x80000000 : 0x7FFFFFFF; +} + +int +test04 (int a) +{ + return ((a & 0x55) == 0) ? 0x7FFFFFFF : 0x80000000; +} + +int +test04_inv (int a) +{ + return ((a & 0x55) != 0) ? 0x80000000 : 0x7FFFFFFF; +} -- 2.7.4