From 91801f68aa27602c2cd5f5dacac7082ed5277677 Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Sat, 18 Nov 2017 04:28:56 +0000
Subject: [PATCH] [AArch64][RegisterBankInfo] Teach instruction mapping about
 gpr32 -> fpr16 cross copies

Turns out this copies can actually occur because of the way we lower the
ABI for half.

llvm-svn: 318586
---
 .../Target/AArch64/AArch64GenRegisterBankInfo.def  |  9 ++++---
 .../AArch64/GlobalISel/arm64-regbankselect.mir     | 29 ++++++++++++++++++++++
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
index 39f50ad..37720cb 100644
--- a/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
+++ b/llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
@@ -72,10 +72,11 @@ RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
     // Cross register bank copies.
-    // 25: FPR 16-bit value to GPR 16-bit (invalid). <-- This must match
-    //                                               FirstCrossRegCpyIdx.
-    {nullptr, 1},
-    {nullptr, 1},
+    // 25: FPR 16-bit value to GPR 16-bit. <-- This must match
+    //                                         FirstCrossRegCpyIdx.
+    // Note: This is the kind of copy we see with physical registers.
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
+    {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
     // 27: FPR 32-bit value to GPR 32-bit value.
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
     {&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index cc158a2..fb02189 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -69,6 +69,7 @@
   define void @bitcast_s128() { ret void }
   define void @copy_s128() { ret void }
   define void @copy_s128_from_load() { ret void }
+  define void @copy_fp16() { ret void }
 
   define i64 @greedyWithChainOfComputation(i64 %arg1, <2 x i32>* %addr) {
     %varg1 = bitcast i64 %arg1 to <2 x i32>
@@ -624,6 +625,34 @@ body:             |
 
 ...
 
+---
+# CHECK-LABEL: name: copy_fp16
+# This test checks that we issue the proper mapping
+# for copy of size == 16 when the destination is a fpr
+# physical register and the source a gpr.
+# We used to crash because we thought that mapping couldn't
+# exist in a copy.
+name:            copy_fp16
+legalized: true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _}
+  - { id: 1, class: _}
+# CHECK: registers:
+# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
+# CHECK: %0:gpr(s32) = COPY %w0
+# CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)
+body:             |
+  bb.1:
+    liveins: %w0
+    %0(s32) = COPY %w0
+    %1(s16) = G_TRUNC %0(s32)
+    %h0 = COPY %1(s16)
+    RET_ReallyLR implicit %h0
+
+...
+
 
 ---
 # Make sure the greedy mode is able to take advantage of the
-- 
2.7.4