From 9161d474763335fab36f31c21824df2a811ed098 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 30 Dec 2014 18:58:47 +0000 Subject: [PATCH] [Hexagon] Adding reg-reg indexed load forms. llvm-svn: 224997 --- llvm/lib/Target/Hexagon/Hexagon.td | 10 ++ llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 48 +++--- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 162 +++++++++++++-------- llvm/test/CodeGen/Hexagon/block-addr.ll | 2 +- .../CodeGen/Hexagon/idxload-with-zero-offset.ll | 12 +- llvm/test/MC/Disassembler/Hexagon/ld.txt | 76 +++++++++- 6 files changed, 216 insertions(+), 94 deletions(-) diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 5f4a6c6..77c21bd 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -50,6 +50,8 @@ def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">; //===----------------------------------------------------------------------===// // Classes used for relation maps. //===----------------------------------------------------------------------===// + +class ImmRegShl; // PredRel - Filter class used to relate non-predicated instructions with their // predicated forms. class PredRel; @@ -180,6 +182,14 @@ def getRegForm : InstrMapping { let ValueCols = [["reg"]]; } +def getRegShlForm : InstrMapping { + let FilterClass = "ImmRegShl"; + let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; + let ColFields = ["InputType"]; + let KeyCol = ["imm"]; + let ValueCols = [["reg"]]; +} + //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index fafc250..ffc59d2 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1351,31 +1351,31 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::L2_ploadrubt_io: case Hexagon::L2_ploadrubf_io: return true; - case Hexagon::L2_ploadrdt_pi : - case Hexagon::L2_ploadrdf_pi : - case Hexagon::L2_ploadrit_pi : - case Hexagon::L2_ploadrif_pi : - case Hexagon::L2_ploadrht_pi : - case Hexagon::L2_ploadrhf_pi : - case Hexagon::L2_ploadrbt_pi : - case Hexagon::L2_ploadrbf_pi : - case Hexagon::L2_ploadruht_pi : - case Hexagon::L2_ploadruhf_pi : - case Hexagon::L2_ploadrubt_pi : - case Hexagon::L2_ploadrubf_pi : + case Hexagon::L2_ploadrdt_pi: + case Hexagon::L2_ploadrdf_pi: + case Hexagon::L2_ploadrit_pi: + case Hexagon::L2_ploadrif_pi: + case Hexagon::L2_ploadrht_pi: + case Hexagon::L2_ploadrhf_pi: + case Hexagon::L2_ploadrbt_pi: + case Hexagon::L2_ploadrbf_pi: + case Hexagon::L2_ploadruht_pi: + case Hexagon::L2_ploadruhf_pi: + case Hexagon::L2_ploadrubt_pi: + case Hexagon::L2_ploadrubf_pi: return QRI.Subtarget.hasV4TOps(); - case Hexagon::LDrid_indexed_shl_cPt_V4 : - case Hexagon::LDrid_indexed_shl_cNotPt_V4 : - case Hexagon::LDrib_indexed_shl_cPt_V4 : - case Hexagon::LDrib_indexed_shl_cNotPt_V4 : - case Hexagon::LDriub_indexed_shl_cPt_V4 : - case Hexagon::LDriub_indexed_shl_cNotPt_V4 : - case Hexagon::LDrih_indexed_shl_cPt_V4 : - case Hexagon::LDrih_indexed_shl_cNotPt_V4 : - case Hexagon::LDriuh_indexed_shl_cPt_V4 : - case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : - case Hexagon::LDriw_indexed_shl_cPt_V4 : - case Hexagon::LDriw_indexed_shl_cNotPt_V4 : + case Hexagon::L4_ploadrdt_rr: + case Hexagon::L4_ploadrdf_rr: + case Hexagon::L4_ploadrbt_rr: + case Hexagon::L4_ploadrbf_rr: + case Hexagon::L4_ploadrubt_rr: + case Hexagon::L4_ploadrubf_rr: + case Hexagon::L4_ploadrht_rr: + case Hexagon::L4_ploadrhf_rr: + case Hexagon::L4_ploadruht_rr: + case Hexagon::L4_ploadruhf_rr: + case Hexagon::L4_ploadrit_rr: + case Hexagon::L4_ploadrif_rr: return QRI.Subtarget.hasV4TOps(); } } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index a92c1a9..894d67d 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -342,112 +342,152 @@ def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>; def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>; def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>; +//===----------------------------------------------------------------------===// +// Template classes for the non-predicated load instructions with +// base + register offset addressing mode +//===----------------------------------------------------------------------===// +class T_load_rr MajOp>: + LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2), + "$dst = "#mnemonic#"($src1 + $src2<<#$u2)", + [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel { + bits<5> dst; + bits<5> src1; + bits<5> src2; + bits<2> u2; -// multiclass for load instructions with base + register offset -// addressing mode -multiclass ld_idxd_shl_pbase { - let isPredicatedNew = isPredNew in - def NAME : LDInst2<(outs RC:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)", - []>, Requires<[HasV4T]>; -} + let IClass = 0b0011; -multiclass ld_idxd_shl_pred { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ld_idxd_shl_pbase; - // Predicate new - defm _cdn#NAME : ld_idxd_shl_pbase; + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{20-16} = src1; + let Inst{12-8} = src2; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{4-0} = dst; } -} -let hasSideEffects = 0 in -multiclass ld_idxd_shl { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { +//===----------------------------------------------------------------------===// +// Template classes for the predicated load instructions with +// base + register offset addressing mode +//===----------------------------------------------------------------------===// +let isPredicated = 1 in +class T_pload_rr MajOp, + bit isNot, bit isPredNew>: + LDInst <(outs RC:$dst), + (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2), + !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)", + [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel { + bits<5> dst; + bits<2> src1; + bits<5> src2; + bits<5> src3; + bits<2> u2; + + let isPredicatedFalse = isNot; + let isPredicatedNew = isPredNew; + + let IClass = 0b0011; + + let Inst{27-26} = 0b00; + let Inst{25} = isPredNew; + let Inst{24} = isNot; + let Inst{23-21} = MajOp; + let Inst{20-16} = src2; + let Inst{12-8} = src3; + let Inst{13} = u2{1}; + let Inst{7} = u2{0}; + let Inst{6-5} = src1; + let Inst{4-0} = dst; + } + +//===----------------------------------------------------------------------===// +// multiclass for load instructions with base + register offset +// addressing mode +//===----------------------------------------------------------------------===// +let hasSideEffects = 0, addrMode = BaseRegOffset in +multiclass ld_idxd_shl MajOp > { + let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl, + InputType = "reg" in { let isPredicable = 1 in - def NAME#_V4 : LDInst2<(outs RC:$dst), - (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset), - "$dst = "#mnemonic#"($src1+$src2<<#$offset)", - []>, Requires<[HasV4T]>; + def L4_#NAME#_rr : T_load_rr ; - let isPredicated = 1 in { - defm Pt_V4 : ld_idxd_shl_pred; - defm NotPt_V4 : ld_idxd_shl_pred; - } + // Predicated + def L4_p#NAME#t_rr : T_pload_rr ; + def L4_p#NAME#f_rr : T_pload_rr ; + + // Predicated new + def L4_p#NAME#tnew_rr : T_pload_rr ; + def L4_p#NAME#fnew_rr : T_pload_rr ; } } -let addrMode = BaseRegOffset in { - let accessSize = ByteAccess in { - defm LDrib_indexed_shl: ld_idxd_shl<"memb", "LDrib", IntRegs>, - AddrModeRel; - defm LDriub_indexed_shl: ld_idxd_shl<"memub", "LDriub", IntRegs>, - AddrModeRel; - } - let accessSize = HalfWordAccess in { - defm LDrih_indexed_shl: ld_idxd_shl<"memh", "LDrih", IntRegs>, AddrModeRel; - defm LDriuh_indexed_shl: ld_idxd_shl<"memuh", "LDriuh", IntRegs>, - AddrModeRel; - } - let accessSize = WordAccess in - defm LDriw_indexed_shl: ld_idxd_shl<"memw", "LDriw", IntRegs>, AddrModeRel; +let hasNewValue = 1, accessSize = ByteAccess, isCodeGenOnly = 0 in { + defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>; + defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>; +} - let accessSize = DoubleWordAccess in - defm LDrid_indexed_shl: ld_idxd_shl<"memd", "LDrid", DoubleRegs>, - AddrModeRel; +let hasNewValue = 1, accessSize = HalfWordAccess, isCodeGenOnly = 0 in { + defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>; + defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>; } +let hasNewValue = 1, accessSize = WordAccess, isCodeGenOnly = 0 in +defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>; + +let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in +defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>; + // 'def pats' for load instructions with base + register offset and non-zero // immediate value. Immediate value is used to left-shift the second // register operand. let AddedComplexity = 40 in { def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDrib_indexed_shl_V4 IntRegs:$src1, + (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDriub_indexed_shl_V4 IntRegs:$src1, + (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (extloadi8 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDriub_indexed_shl_V4 IntRegs:$src1, + (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDrih_indexed_shl_V4 IntRegs:$src1, + (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDriuh_indexed_shl_V4 IntRegs:$src1, + (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (extloadi16 (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDriuh_indexed_shl_V4 IntRegs:$src1, + (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i32 (load (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDriw_indexed_shl_V4 IntRegs:$src1, + (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; def : Pat <(i64 (load (add IntRegs:$src1, (shl IntRegs:$src2, u2ImmPred:$offset)))), - (LDrid_indexed_shl_V4 IntRegs:$src1, + (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, u2ImmPred:$offset)>, Requires<[HasV4T]>; } @@ -457,35 +497,35 @@ def : Pat <(i64 (load (add IntRegs:$src1, // zero immediate value. let AddedComplexity = 10 in { def : Pat <(i64 (load (add IntRegs:$src1, IntRegs:$src2))), - (LDrid_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadrd_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (sextloadi8 (add IntRegs:$src1, IntRegs:$src2))), - (LDrib_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadrb_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (zextloadi8 (add IntRegs:$src1, IntRegs:$src2))), - (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (extloadi8 (add IntRegs:$src1, IntRegs:$src2))), - (LDriub_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadrub_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (sextloadi16 (add IntRegs:$src1, IntRegs:$src2))), - (LDrih_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadrh_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (zextloadi16 (add IntRegs:$src1, IntRegs:$src2))), - (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (extloadi16 (add IntRegs:$src1, IntRegs:$src2))), - (LDriuh_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadruh_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; def : Pat <(i32 (load (add IntRegs:$src1, IntRegs:$src2))), - (LDriw_indexed_shl_V4 IntRegs:$src1, IntRegs:$src2, 0)>, + (L4_loadri_rr IntRegs:$src1, IntRegs:$src2, 0)>, Requires<[HasV4T]>; } diff --git a/llvm/test/CodeGen/Hexagon/block-addr.ll b/llvm/test/CodeGen/Hexagon/block-addr.ll index 54a12bf..dc0d6e6 100644 --- a/llvm/test/CodeGen/Hexagon/block-addr.ll +++ b/llvm/test/CodeGen/Hexagon/block-addr.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = CONST32(#.LJTI{{[0-9]+_[0-9]+}}) -; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+<<#[0-9]+}}) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}} + r{{[0-9]+<<#[0-9]+}}) ; CHECK: jumpr r{{[0-9]+}} define void @main() #0 { diff --git a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index ca6df88..729d79f5 100644 --- a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -4,7 +4,7 @@ ; load word define i32 @load_w(i32* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i32* %a, i32 %tmp @@ -15,7 +15,7 @@ entry: ; load unsigned half word define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i16* %a, i32 %tmp @@ -26,7 +26,7 @@ entry: ; load signed half word define i32 @load_h(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i16* %a, i32 %tmp @@ -38,7 +38,7 @@ entry: ; load unsigned byte define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i8* %a, i32 %tmp @@ -49,7 +49,7 @@ entry: ; load signed byte define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i8* %a, i32 %tmp @@ -61,7 +61,7 @@ entry: ; load doubleword define i64 @load_d(i64* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) entry: %tmp = shl i32 %n, 4 %scevgep9 = getelementptr i64* %a, i32 %tmp diff --git a/llvm/test/MC/Disassembler/Hexagon/ld.txt b/llvm/test/MC/Disassembler/Hexagon/ld.txt index 041dcf8..313bf7ab 100644 --- a/llvm/test/MC/Disassembler/Hexagon/ld.txt +++ b/llvm/test/MC/Disassembler/Hexagon/ld.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s -0x70 0xd8 0xd5 0x41 -# CHECK: if (p3) r17:16 = memd(r21 + #24) +0x90 0xff 0xd5 0x3a +# CHECK: r17:16 = memd(r21 + r31<<#3) 0xb0 0xe0 0xd5 0x99 # CHECK: r17:16 = memd(r21 ++ #40:circ(m1)) 0x10 0xe2 0xd5 0x99 @@ -12,6 +12,18 @@ # CHECK: r17:16 = memd(r21++m1) 0x10 0xe0 0xd5 0x9f # CHECK: r17:16 = memd(r21 ++ m1:brev) +0xf0 0xff 0xd5 0x30 +# CHECK: if (p3) r17:16 = memd(r21+r31<<#3) +0xf0 0xff 0xd5 0x31 +# CHECK: if (!p3) r17:16 = memd(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf0 0xff 0xd5 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17:16 = memd(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf0 0xff 0xd5 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+r31<<#3) +0x70 0xd8 0xd5 0x41 +# CHECK: if (p3) r17:16 = memd(r21 + #24) 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43 # CHECK: p3 = r5 # CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24) @@ -31,6 +43,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40) +0x91 0xff 0x15 0x3a +# CHECK: r17 = memb(r21 + r31<<#3) 0xf1 0xc3 0x15 0x91 # CHECK: r17 = memb(r21 + #31) 0xb1 0xe0 0x15 0x99 @@ -43,6 +57,16 @@ # CHECK: r17 = memb(r21++m1) 0x11 0xe0 0x15 0x9f # CHECK: r17 = memb(r21 ++ m1:brev) +0xf1 0xff 0x15 0x30 +# CHECK: if (p3) r17 = memb(r21+r31<<#3) +0xf1 0xff 0x15 0x31 +# CHECK: if (!p3) r17 = memb(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memb(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memb(r21+r31<<#3) 0x91 0xdd 0x15 0x41 # CHECK: if (p3) r17 = memb(r21 + #44) 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43 @@ -64,6 +88,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5) +0x91 0xff 0x55 0x3a +# CHECK: r17 = memh(r21 + r31<<#3) 0xf1 0xc3 0x55 0x91 # CHECK: r17 = memh(r21 + #62) 0xb1 0xe0 0x55 0x99 @@ -76,6 +102,16 @@ # CHECK: r17 = memh(r21++m1) 0x11 0xe0 0x55 0x9f # CHECK: r17 = memh(r21 ++ m1:brev) +0xf1 0xff 0x55 0x30 +# CHECK: if (p3) r17 = memh(r21+r31<<#3) +0xf1 0xff 0x55 0x31 +# CHECK: if (!p3) r17 = memh(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x55 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memh(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x55 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memh(r21+r31<<#3) 0xb1 0xe6 0x55 0x9b # CHECK: if (p3) r17 = memh(r21++#10) 0xb1 0xee 0x55 0x9b @@ -87,6 +123,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10) +0x91 0xff 0x35 0x3a +# CHECK: r17 = memub(r21 + r31<<#3) 0xf1 0xc3 0x35 0x91 # CHECK: r17 = memub(r21 + #31) 0xb1 0xe0 0x35 0x99 @@ -99,6 +137,16 @@ # CHECK: r17 = memub(r21++m1) 0x11 0xe0 0x35 0x9f # CHECK: r17 = memub(r21 ++ m1:brev) +0xf1 0xff 0x35 0x30 +# CHECK: if (p3) r17 = memub(r21+r31<<#3) +0xf1 0xff 0x35 0x31 +# CHECK: if (!p3) r17 = memub(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memub(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memub(r21+r31<<#3) 0xf1 0xdb 0x35 0x41 # CHECK: if (p3) r17 = memub(r21 + #31) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43 @@ -120,6 +168,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5) +0x91 0xff 0x75 0x3a +# CHECK: r17 = memuh(r21 + r31<<#3) 0xb1 0xc2 0x75 0x91 # CHECK: r17 = memuh(r21 + #42) 0xb1 0xe0 0x75 0x99 @@ -132,6 +182,16 @@ # CHECK: r17 = memuh(r21++m1) 0x11 0xe0 0x75 0x9f # CHECK: r17 = memuh(r21 ++ m1:brev) +0xf1 0xff 0x75 0x30 +# CHECK: if (p3) r17 = memuh(r21+r31<<#3) +0xf1 0xff 0x75 0x31 +# CHECK: if (!p3) r17 = memuh(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memuh(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memuh(r21+r31<<#3) 0xb1 0xda 0x75 0x41 # CHECK: if (p3) r17 = memuh(r21 + #42) 0xb1 0xda 0x75 0x45 @@ -153,6 +213,8 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10) +0x91 0xff 0x95 0x3a +# CHECK: r17 = memw(r21 + r31<<#3) 0xb1 0xc2 0x95 0x91 # CHECK: r17 = memw(r21 + #84) 0xb1 0xe0 0x95 0x99 @@ -165,6 +227,16 @@ # CHECK: r17 = memw(r21++m1) 0x11 0xe0 0x95 0x9f # CHECK: r17 = memw(r21 ++ m1:brev) +0xf1 0xff 0x95 0x30 +# CHECK: if (p3) r17 = memw(r21+r31<<#3) +0xf1 0xff 0x95 0x31 +# CHECK: if (!p3) r17 = memw(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x95 0x32 +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = memw(r21+r31<<#3) +0x03 0x40 0x45 0x85 0xf1 0xff 0x95 0x33 +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = memw(r21+r31<<#3) 0xb1 0xda 0x95 0x41 # CHECK: if (p3) r17 = memw(r21 + #84) 0xb1 0xda 0x95 0x45 -- 2.7.4