From 914da438d9e68034c7376a5558386b494a35c514 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Tue, 11 May 2010 12:59:06 -0700 Subject: [PATCH] com32: Unbreak CPUID functions were apparently broken when made PIC-safe; clean up and fix. Signed-off-by: H. Peter Anvin --- com32/include/sys/cpu.h | 83 ++++++++++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 32 deletions(-) diff --git a/com32/include/sys/cpu.h b/com32/include/sys/cpu.h index a798a84..53a6250 100644 --- a/com32/include/sys/cpu.h +++ b/com32/include/sys/cpu.h @@ -8,14 +8,14 @@ static inline uint64_t rdtsc(void) { uint64_t v; - asm volatile ("rdtsc":"=A" (v)); + asm volatile("rdtsc" : "=A" (v)); return v; } static inline uint32_t rdtscl(void) { uint32_t v; - asm volatile ("rdtsc":"=a" (v)::"edx"); + asm volatile("rdtsc" : "=a" (v) : : "edx"); return v; } @@ -23,26 +23,29 @@ static inline void cpuid_count(uint32_t op, uint32_t cnt, uint32_t * eax, uint32_t * ebx, uint32_t * ecx, uint32_t * edx) { -asm("pushl %%ebx ; cpuid ; movl %%ebx,%0 ; popl %%ebx":"=a"(*eax), "=SD"(*ebx), "=c"(*ecx), - "=d"(*edx) -: "a"(op), "c"(cnt)); + asm volatile("movl %%ebx,%1 ; " + "cpuid ; " + "xchgl %1,%%ebx" + : "=a" (*eax), "=SD" (*ebx), "=c" (*ecx), "=d" (*edx) + : "a"(op), "c"(cnt)); } static inline void cpuid(uint32_t op, uint32_t * eax, uint32_t * ebx, uint32_t * ecx, uint32_t * edx) { -asm("pushl %%ebx ; cpuid ; movl %%ebx,%0 ; popl %%ebx":"=a"(*eax), "=SD"(*ebx), "=c"(*ecx), - "=d"(*edx) -: "a"(op)); + cpuid_count(op, 0, eax, ebx, ecx, edx); } static inline __constfunc uint32_t cpuid_eax(uint32_t level) { uint32_t v; -asm("pushl %%ebx ; cpuid ; popl %%ebx":"=a"(v) -: "a"(level) -: "ecx", "edx"); + asm volatile("pushl %%ebx ; " + "cpuid ; " + "popl %%ebx" + : "=a" (v) + : "a"(level) + : "ecx", "edx"); return v; } @@ -50,9 +53,11 @@ static inline __constfunc uint32_t cpuid_ebx(uint32_t level) { uint32_t v; -asm("pushl %%ebx ; cpuid ; movl %%ebx,%0 ; popl %%ebx":"=a"(v) -: "a"(level) -: "ecx", "edx"); + asm volatile("movl %%ebx,%0 ; " + "cpuid ; " + "xchgl %0,%%ebx" + : "=SD" (v), "+a" (level) + : : "ecx", "edx"); return v; } @@ -60,8 +65,11 @@ static inline __constfunc uint32_t cpuid_ecx(uint32_t level) { uint32_t v; -asm("pushl %%ebx ; cpuid ; popl %%ebx":"=c"(v), "+a"(level) -: : "edx"); + asm volatile("pushl %%ebx ; " + "cpuid ; " + "popl %%ebx" + : "=c" (v), "+a" (level) + : : "edx"); return v; } @@ -69,55 +77,66 @@ static inline __constfunc uint32_t cpuid_edx(uint32_t level) { uint32_t v; -asm("pushl %%ebx ; cpuid ; popl %%ebx":"=d"(v), "+a"(level) -: : "ecx"); + asm volatile("pushl %%ebx ; " + "cpuid ; " + "popl %%ebx" + : "=d" (v), "+a" (level) + : : "ecx"); return v; } /* Standard macro to see if a specific flag is changeable */ static inline __constfunc bool cpu_has_eflag(uint32_t flag) { - uint32_t f1, f2; - -asm("pushfl\n\t" "pushfl\n\t" "popl %0\n\t" "movl %0,%1\n\t" "xorl %2,%0\n\t" "pushl %0\n\t" "popfl\n\t" "pushfl\n\t" "popl %0\n\t" "popfl\n\t":"=&r"(f1), - "=&r" - (f2) -: "ir"(flag)); - - return ((f1 ^ f2) & flag) != 0; + uint32_t f0, f1; + + asm("pushfl ; " + "pushfl ; " + "popl %0 ; " + "movl %0,%1 ; " + "xorl %2,%1 ; " + "pushl %1 ; " + "popfl ; " + "pushfl ; " + "popl %1 ; " + "popfl" + : "=&r" (f0), "=&r" (f1) + : "ri" (flag)); + + return !!((f0^f1) & flag); } static inline uint64_t rdmsr(uint32_t msr) { uint64_t v; - asm volatile ("rdmsr":"=A" (v):"c"(msr)); + asm volatile("rdmsr" : "=A" (v) : "c"(msr)); return v; } static inline void wrmsr(uint64_t v, uint32_t msr) { - asm volatile ("wrmsr"::"A" (v), "c"(msr)); + asm volatile("wrmsr" : : "A" (v), "c" (msr)); } static inline void cpu_relax(void) { - asm volatile ("rep ; nop"); + asm volatile("rep ; nop"); } static inline void hlt(void) { - asm volatile ("hlt"); + asm volatile("hlt"); } static inline void cli(void) { - asm volatile ("cli"); + asm volatile("cli"); } static inline void sti(void) { - asm volatile ("sti"); + asm volatile("sti"); } #endif -- 2.7.4