From 9123f82cc41094fbee47fd53c068b5c2d340f264 Mon Sep 17 00:00:00 2001 From: "Diogo N. Sampaio" Date: Fri, 28 Dec 2018 17:14:58 +0000 Subject: [PATCH] [AArch64] Add command-line option for SB SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also moves to FeatureSB the old FeatureSpecRestrict. Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55921 llvm-svn: 350126 --- llvm/include/llvm/Support/AArch64TargetParser.def | 1 + llvm/include/llvm/Support/AArch64TargetParser.h | 1 + llvm/lib/Target/AArch64/AArch64.td | 8 ++++---- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 +++--- llvm/lib/Target/AArch64/AArch64Subtarget.h | 4 ++-- llvm/test/MC/AArch64/{armv8.5a-specctrl.s => armv8.5a-sb.s} | 8 ++++---- llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt | 9 +++++++++ llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt | 9 --------- llvm/unittests/Support/TargetParserTest.cpp | 3 ++- 9 files changed, 26 insertions(+), 23 deletions(-) rename llvm/test/MC/AArch64/{armv8.5a-specctrl.s => armv8.5a-sb.s} (59%) create mode 100644 llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt delete mode 100644 llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def index 6a7d16a..1493b7a 100644 --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -73,6 +73,7 @@ AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc") AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand") AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") +AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h index aea4062..648aa94 100644 --- a/llvm/include/llvm/Support/AArch64TargetParser.h +++ b/llvm/include/llvm/Support/AArch64TargetParser.h @@ -48,6 +48,7 @@ enum ArchExtKind : unsigned { AEK_RAND = 1 << 18, AEK_MTE = 1 << 19, AEK_SSBS = 1 << 20, + AEK_SB = 1 << 21, }; enum class ArchKind { diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index a13f6c8..e6da78d 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -306,12 +306,12 @@ def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", "true", "Enable architectural speculation restriction" >; +def FeatureSB : SubtargetFeature<"sb", "HasSB", + "true", "Enable v8.5 Speculation Barrier" >; + def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", "true", "Enable Speculative Store Bypass Safe bit" >; -def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true", - "Enable speculation control barrier" >; - def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true", "Enable execution and data prediction invalidation instructions" >; @@ -352,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", def HasV8_5aOps : SubtargetFeature< "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, - FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist, + FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist, FeatureBranchTargetId] >; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index eb972b5..67a2095 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -114,8 +114,8 @@ def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">; def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">, AssemblerPredicate<"FeatureFRInt3264", "frint3264">; -def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">, - AssemblerPredicate<"FeatureSpecCtrl", "specctrl">; +def HasSB : Predicate<"Subtarget->hasSB()">, + AssemblerPredicate<"FeatureSB", "sb">; def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">, AssemblerPredicate<"FeaturePredCtrl", "predctrl">; def HasCCDP : Predicate<"Subtarget->hasCCDP()">, @@ -733,7 +733,7 @@ def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> { def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> { let Inst{20-5} = 0b0001100110000111; let Unpredictable{11-8} = 0b1111; - let Predicates = [HasSpecCtrl]; + let Predicates = [HasSB]; let hasSideEffects = 1; } diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 9b27e0a..e94a044 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -126,8 +126,8 @@ protected: bool HasAlternativeNZCV = false; bool HasFRInt3264 = false; bool HasSpecRestrict = false; - bool HasSpecCtrl = false; bool HasSSBS = false; + bool HasSB = false; bool HasPredCtrl = false; bool HasCCDP = false; bool HasBTI = false; @@ -355,8 +355,8 @@ public: bool hasAlternativeNZCV() const { return HasAlternativeNZCV; } bool hasFRInt3264() const { return HasFRInt3264; } bool hasSpecRestrict() const { return HasSpecRestrict; } - bool hasSpecCtrl() const { return HasSpecCtrl; } bool hasSSBS() const { return HasSSBS; } + bool hasSB() const { return HasSB; } bool hasPredCtrl() const { return HasPredCtrl; } bool hasCCDP() const { return HasCCDP; } bool hasBTI() const { return HasBTI; } diff --git a/llvm/test/MC/AArch64/armv8.5a-specctrl.s b/llvm/test/MC/AArch64/armv8.5a-sb.s similarity index 59% rename from llvm/test/MC/AArch64/armv8.5a-specctrl.s rename to llvm/test/MC/AArch64/armv8.5a-sb.s index 279a396..7d88aed 100644 --- a/llvm/test/MC/AArch64/armv8.5a-specctrl.s +++ b/llvm/test/MC/AArch64/armv8.5a-sb.s @@ -1,11 +1,11 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sb -o - %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a -o - %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-sb -o - %s 2>&1 | FileCheck %s --check-prefix=NOSB // Flag manipulation sb // CHECK: sb // encoding: [0xff,0x30,0x03,0xd5] -// NOSB: instruction requires: specctrl +// NOSB: instruction requires: sb // NOSB-NEXT: sb diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt new file mode 100644 index 0000000..25f32d4 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-sb.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB + +# New reg +0xff 0x30 0x03 0xd5 + +# CHECK: sb +# NOSB: msr S0_3_C3_C0_7, xzr diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt deleted file mode 100644 index d2174ae..0000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt +++ /dev/null @@ -1,9 +0,0 @@ -# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB - -# New reg -0xff 0x30 0x03 0xd5 - -# CHECK: sb -# NOSB: msr S0_3_C3_C0_7, xzr diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index a6a6150..7fc51ae 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -988,7 +988,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) { {"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rng", "norng", "+rand", "-rand"}, {"memtag", "nomemtag", "+mte", "-mte"}, - {"ssbs", "nossbs", "+ssbs", "-ssbs"}}; + {"ssbs", "nossbs", "+ssbs", "-ssbs"}, + {"sb", "nosb", "+sb", "-sb"}}; for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]), -- 2.7.4