From 907f5f0ca75dd7c45191ce81bd483e8198b2d4d2 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri, 16 Nov 2012 02:39:34 +0000
Subject: [PATCH] [mips] Fix delay slot filler so that instructions with
 register operand $1 are allowed in branch delay slot.

llvm-svn: 168131
---
 llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 51 ++++++++++++++++++----------
 llvm/test/CodeGen/Mips/brdelayslot.ll        | 32 +++++++++++++++++
 2 files changed, 66 insertions(+), 17 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index e3c8ed7..17a19fb 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -231,31 +231,48 @@ bool Filler::delayHasHazard(InstrIter candidate,
   return false;
 }
 
+// Helper function for getting a MachineOperand's register number and adding it
+// to RegDefs or RegUses.
+static void insertDefUse(const MachineOperand &MO,
+                         SmallSet<unsigned, 32> &RegDefs,
+                         SmallSet<unsigned, 32> &RegUses,
+                         unsigned ExcludedReg = 0) {
+  unsigned Reg;
+
+  if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
+    return;
+
+  if (MO.isDef())
+    RegDefs.insert(Reg);
+  else if (MO.isUse())
+    RegUses.insert(Reg);
+}
+
 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
 void Filler::insertDefsUses(InstrIter MI,
                             SmallSet<unsigned, 32> &RegDefs,
                             SmallSet<unsigned, 32> &RegUses) {
-  // If MI is a call or return, just examine the explicit non-variadic operands.
-  MCInstrDesc MCID = MI->getDesc();
-  unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
-                                                MI->getNumOperands();
+  unsigned I, E = MI->getDesc().getNumOperands();
 
-  // Add RA to RegDefs to prevent users of RA from going into delay slot.
-  if (MI->isCall())
-    RegDefs.insert(Mips::RA);
+  for (I = 0; I != E; ++I)
+    insertDefUse(MI->getOperand(I), RegDefs, RegUses);
 
-  for (unsigned i = 0; i != e; ++i) {
-    const MachineOperand &MO = MI->getOperand(i);
-    unsigned Reg;
+  // If MI is a call, add RA to RegDefs to prevent users of RA from going into
+  // delay slot.
+  if (MI->isCall()) {
+    RegDefs.insert(Mips::RA);
+    return;
+  }
 
-    if (!MO.isReg() || !(Reg = MO.getReg()))
-      continue;
+  // Return if MI is a return.
+  if (MI->isReturn())
+    return;
 
-    if (MO.isDef())
-      RegDefs.insert(Reg);
-    else if (MO.isUse())
-      RegUses.insert(Reg);
-  }
+  // Examine the implicit operands. Exclude register AT which is in the list of
+  // clobbered registers of branch instructions.
+  E = MI->getNumOperands();
+  for (; I != E; ++I)
+    insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
 }
 
 //returns true if the Reg or its alias is in the RegSet.
diff --git a/llvm/test/CodeGen/Mips/brdelayslot.ll b/llvm/test/CodeGen/Mips/brdelayslot.ll
index 2fdb736..897fc97 100644
--- a/llvm/test/CodeGen/Mips/brdelayslot.ll
+++ b/llvm/test/CodeGen/Mips/brdelayslot.ll
@@ -35,3 +35,35 @@ entry:
 
 declare void @foo4(double)
 
+@g2 = external global i32
+@g1 = external global i32
+@g3 = external global i32
+
+; Check that branch delay slot can be filled with an instruction with operand
+; $1.
+;
+; Default:     foo5:
+; Default-NOT: nop
+
+define void @foo5(i32 %a) nounwind {
+entry:
+  %0 = load i32* @g2, align 4
+  %tobool = icmp eq i32 %a, 0
+  br i1 %tobool, label %if.else, label %if.then
+
+if.then:
+  %1 = load i32* @g1, align 4
+  %add = add nsw i32 %1, %0
+  store i32 %add, i32* @g1, align 4
+  br label %if.end
+
+if.else:
+  %2 = load i32* @g3, align 4
+  %sub = sub nsw i32 %2, %0
+  store i32 %sub, i32* @g3, align 4
+  br label %if.end
+
+if.end:
+  ret void
+}
+
-- 
2.7.4