From 902157c2497c0806f407d78f63d439cd94fc6136 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 25 Nov 2014 18:20:52 +0000 Subject: [PATCH] [Hexagon] Replacing cmp* instructions with ones that contain encoding bits. llvm-svn: 222771 --- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 6 +- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 18 ++--- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 89 +++++++++++++++--------- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 14 ++-- llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp | 8 +-- llvm/test/MC/Hexagon/inst_cmp_eq.ll | 10 +++ llvm/test/MC/Hexagon/inst_cmp_gt.ll | 10 +++ llvm/test/MC/Hexagon/inst_cmp_lt.ll | 10 +++ llvm/test/MC/Hexagon/inst_cmp_ugt.ll | 10 +++ llvm/test/MC/Hexagon/inst_cmp_ult.ll | 10 +++ 10 files changed, 129 insertions(+), 56 deletions(-) create mode 100644 llvm/test/MC/Hexagon/inst_cmp_eq.ll create mode 100644 llvm/test/MC/Hexagon/inst_cmp_gt.ll create mode 100644 llvm/test/MC/Hexagon/inst_cmp_lt.ll create mode 100644 llvm/test/MC/Hexagon/inst_cmp_ugt.ll create mode 100644 llvm/test/MC/Hexagon/inst_cmp_ult.ll diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 24aacdf..39d4452 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -541,15 +541,15 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, switch (CondOpc) { case Hexagon::CMPEQri: - case Hexagon::CMPEQrr: + case Hexagon::C2_cmpeq: Cmp = !Negated ? Comparison::EQ : Comparison::NE; break; case Hexagon::CMPGTUri: - case Hexagon::CMPGTUrr: + case Hexagon::C2_cmpgtu: Cmp = !Negated ? Comparison::GTu : Comparison::LEu; break; case Hexagon::CMPGTri: - case Hexagon::CMPGTrr: + case Hexagon::C2_cmpgt: Cmp = !Negated ? Comparison::GTs : Comparison::LEs; break; // Very limited support for byte/halfword compares. diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index a44fd93..8d3916e 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -348,13 +348,13 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI, switch (Opc) { case Hexagon::CMPEHexagon4rr: case Hexagon::CMPEQri: - case Hexagon::CMPEQrr: + case Hexagon::C2_cmpeq: case Hexagon::CMPGT64rr: case Hexagon::CMPGTU64rr: case Hexagon::CMPGTUri: - case Hexagon::CMPGTUrr: + case Hexagon::C2_cmpgtu: case Hexagon::CMPGTri: - case Hexagon::CMPGTrr: + case Hexagon::C2_cmpgt: SrcReg = MI->getOperand(1).getReg(); Mask = ~0; break; @@ -381,11 +381,11 @@ bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI, // Set the value/second source register. switch (Opc) { case Hexagon::CMPEHexagon4rr: - case Hexagon::CMPEQrr: + case Hexagon::C2_cmpeq: case Hexagon::CMPGT64rr: case Hexagon::CMPGTU64rr: - case Hexagon::CMPGTUrr: - case Hexagon::CMPGTrr: + case Hexagon::C2_cmpgtu: + case Hexagon::C2_cmpgt: case Hexagon::CMPbEQrr_sbsb_V4: case Hexagon::CMPbEQrr_ubub_V4: case Hexagon::CMPbGTUrr_V4: @@ -1264,11 +1264,11 @@ isSpillPredRegOp(const MachineInstr *MI) const { bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { switch (MI->getOpcode()) { default: return false; - case Hexagon::CMPEQrr: + case Hexagon::C2_cmpeq: case Hexagon::CMPEQri: - case Hexagon::CMPGTrr: + case Hexagon::C2_cmpgt: case Hexagon::CMPGTri: - case Hexagon::CMPGTUrr: + case Hexagon::C2_cmpgtu: case Hexagon::CMPGTUri: return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index b9b03ad..a808100 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -39,12 +39,6 @@ multiclass CMP64_rr { multiclass CMP32_rr_ri_s10 { let CextOpcode = CextOp in { - let InputType = "reg" in - def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c), - !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")), - [(set (i1 PredRegs:$dst), - (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>; - let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10, InputType = "imm" in def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, s10Ext:$c), @@ -56,12 +50,6 @@ multiclass CMP32_rr_ri_s10 { multiclass CMP32_rr_ri_u9 { let CextOpcode = CextOp in { - let InputType = "reg" in - def rr : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c), - !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")), - [(set (i1 PredRegs:$dst), - (OpNode (i32 IntRegs:$b), (i32 IntRegs:$c)))]>; - let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 9, InputType = "imm" in def ri : ALU32_ri<(outs PredRegs:$dst), (ins IntRegs:$b, u9Ext:$c), @@ -624,6 +612,51 @@ def : Pat <(sext_inreg (i32 IntRegs:$src1), i16), // ALU32/PRED + //===----------------------------------------------------------------------===// + +let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in +class T_ALU32_3op_cmp MinOp, bit IsNeg, bit IsComm> + : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), + "$Pd = "#mnemonic#"($Rs, $Rt)", + [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { + let CextOpcode = mnemonic; + let isCommutable = IsComm; + bits<5> Rs; + bits<5> Rt; + bits<2> Pd; + + let IClass = 0b1111; + let Inst{27-24} = 0b0010; + let Inst{22-21} = MinOp; + let Inst{20-16} = Rs; + let Inst{12-8} = Rt; + let Inst{4} = IsNeg; + let Inst{3-2} = 0b00; + let Inst{1-0} = Pd; +} + +let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { + def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; + def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; + def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; +} + +// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones +// that reverse the order of the operands. +class RevCmp : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>; + +// Pats for compares. They use PatFrags as operands, not SDNodes, +// since seteq/setgt/etc. are defined as ParFrags. +class T_cmp32_rr_pat + : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), + (VT (MI IntRegs:$Rs, IntRegs:$Rt))>; + +def: T_cmp32_rr_pat; +def: T_cmp32_rr_pat; +def: T_cmp32_rr_pat; + +def: T_cmp32_rr_pat, i1>; +def: T_cmp32_rr_pat, i1>; + // Compare. defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel; defm CMPGT : CMP32_rr_ri_s10<"cmp.gt", "CMPGT", setgt>, ImmRegRel; @@ -2298,16 +2331,6 @@ def : Pat <(and (i32 IntRegs:$src1), 255), def : Pat <(add (i1 PredRegs:$src1), -1), (NOT_p (i1 PredRegs:$src1))>; -// Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) => -// p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1). -// cmp.lt(r0, r1) -> cmp.gt(r1, r0) -def : Pat <(select (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i32 IntRegs:$src3), - (i32 IntRegs:$src4)), - (i32 (TFR_condset_rr (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), - (i32 IntRegs:$src4), (i32 IntRegs:$src3)))>, - Requires<[HasV2TOnly]>; - // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i). def : Pat <(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ImmPred:$src3), (i32 (TFR_condset_ii (i1 PredRegs:$src1), s8ImmPred:$src3, @@ -2364,7 +2387,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), // Map brcond with an unsupported setcc to a JMP_f. def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), bb:$offset), - (JMP_f (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), + (JMP_f (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>; def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)), @@ -2386,7 +2409,7 @@ def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), // cmp.lt(r0, r1) -> cmp.gt(r1, r0) def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))), bb:$offset), - (JMP_t (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>; + (JMP_t (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>; def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), bb:$offset), @@ -2395,7 +2418,7 @@ def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))), bb:$offset), - (JMP_f (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)), + (JMP_f (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)), bb:$offset)>; def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), @@ -2483,7 +2506,7 @@ def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)), // rs <= rt -> !(rs > rt). def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (NOT_p (CMPGTrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; + (i1 (NOT_p (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; // Rss <= Rtt -> !(Rss > Rtt). def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), @@ -2498,7 +2521,7 @@ def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)), // Map cmpne(Rs) -> !cmpeqe(Rs). // rs != rt -> !(rs == rt). def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (NOT_p (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>; + (i1 (NOT_p (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>; // Convert setne back to xor for hexagon since we compute w/ pred registers. def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))), @@ -2513,7 +2536,7 @@ def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt). // rs >= rt -> !(rt > rs). def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (NOT_p (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>; + (i1 (NOT_p (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>; // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1) def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)), @@ -2535,7 +2558,7 @@ def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)), // rs < rt -> rt > rs. // We can let assembler map it, or we can do in the compiler itself. def : Pat <(i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (CMPGTrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>; + (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>; // Map cmplt(Rss, Rtt) -> cmpgt(Rtt, Rss). // rss < rtt -> (rtt > rss). @@ -2546,7 +2569,7 @@ def : Pat <(i1 (setlt (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), // rs < rt -> rt > rs. // We can let assembler map it, or we can do in the compiler itself. def : Pat <(i1 (setult (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>; + (i1 (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1)))>; // Map from cmpltu(Rss, Rdd) -> cmpgtu(Rdd, Rss). // rs < rt -> rt > rs. @@ -2555,7 +2578,7 @@ def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs) def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)), - (i1 (CMPEQrr (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>; + (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>; // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1) def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)), @@ -2568,7 +2591,7 @@ def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)), // Map from Rs >= Rt -> !(Rt > Rs). // rs >= rt -> !(rt > rs). def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>; + (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>; // Map from Rs >= Rt -> !(Rt > Rs). // rs >= rt -> !(rt > rs). @@ -2578,7 +2601,7 @@ def : Pat <(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), // Map from cmpleu(Rs, Rt) -> !cmpgtu(Rs, Rt). // Map from (Rs <= Rt) -> !(Rs > Rt). def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))), - (i1 (NOT_p (CMPGTUrr (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; + (i1 (NOT_p (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1). // Map from (Rs <= Rt) -> !(Rs > Rt). diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index d39f7d7..f9e4999 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2341,7 +2341,7 @@ def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)), // if (!Pd.new) Rd=#0 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs) def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt), + (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt), (i32 IntRegs:$Rs))), 1, 0))>, Requires<[HasV4T]>; @@ -2354,7 +2354,7 @@ def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (!Pd.new) Rd=#0 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs) def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt), + (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt), (i32 IntRegs:$Rs))), 1, 0))>, Requires<[HasV4T]>; @@ -2366,7 +2366,7 @@ def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (Pd.new) Rd=#1 // if (!Pd.new) Rd=#0 def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs), + (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 1, 0))>, Requires<[HasV4T]>; @@ -2388,7 +2388,7 @@ def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (!Pd.new) Rd=#1 // cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs) def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt), + (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt), (i32 IntRegs:$Rs))), 0, 1))>, Requires<[HasV4T]>; @@ -2401,7 +2401,7 @@ def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (!Pd.new) Rd=#1 // cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs) def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt), + (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt), (i32 IntRegs:$Rs))), 0, 1))>, Requires<[HasV4T]>; @@ -2413,7 +2413,7 @@ def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (Pd.new) Rd=#0 // if (!Pd.new) Rd=#1 def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs), + (i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 0, 1))>, Requires<[HasV4T]>; @@ -2425,7 +2425,7 @@ def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), // if (Pd.new) Rd=#0 // if (!Pd.new) Rd=#1 def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))), - (i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs), + (i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 0, 1))>, Requires<[HasV4T]>; diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 782c979..25d6c68 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -299,7 +299,7 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, taken = true; switch (MI->getOpcode()) { - case Hexagon::CMPEQrr: + case Hexagon::C2_cmpeq: return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4 : Hexagon::CMPEQrr_t_Jumpnv_nt_V4; @@ -312,7 +312,7 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, : Hexagon::CMPEQn1_t_Jumpnv_nt_V4; } - case Hexagon::CMPGTrr: { + case Hexagon::C2_cmpgt: { if (secondRegNewified) return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4 : Hexagon::CMPLTrr_t_Jumpnv_nt_V4; @@ -330,7 +330,7 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg, : Hexagon::CMPGTn1_t_Jumpnv_nt_V4; } - case Hexagon::CMPGTUrr: { + case Hexagon::C2_cmpgtu: { if (secondRegNewified) return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4 : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4; @@ -545,7 +545,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { if (isSecondOpReg) { // In case of CMPLT, or CMPLTU, or EQ with the second register // to newify, swap the operands. - if (cmpInstr->getOpcode() == Hexagon::CMPEQrr && + if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq && feederReg == (unsigned) cmpOp2) { unsigned tmp = cmpReg1; bool tmpIsKill = MO1IsKill; diff --git a/llvm/test/MC/Hexagon/inst_cmp_eq.ll b/llvm/test/MC/Hexagon/inst_cmp_eq.ll new file mode 100644 index 0000000..11a06a4 --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_cmp_eq.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i1 @foo (i32 %a, i32 %b) +{ + %1 = icmp eq i32 %a, %b + ret i1 %1 +} + +; CHECK: 0000 004100f2 00400000 00c09f52 \ No newline at end of file diff --git a/llvm/test/MC/Hexagon/inst_cmp_gt.ll b/llvm/test/MC/Hexagon/inst_cmp_gt.ll new file mode 100644 index 0000000..4ec1ce9 --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_cmp_gt.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i1 @foo (i32 %a, i32 %b) +{ + %1 = icmp sgt i32 %a, %b + ret i1 %1 +} + +; CHECK: 0000 004140f2 00400000 00c09f52 \ No newline at end of file diff --git a/llvm/test/MC/Hexagon/inst_cmp_lt.ll b/llvm/test/MC/Hexagon/inst_cmp_lt.ll new file mode 100644 index 0000000..9f156ed --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_cmp_lt.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i1 @foo (i32 %a, i32 %b) +{ + %1 = icmp slt i32 %a, %b + ret i1 %1 +} + +; CHECK: 0000 004041f2 00400000 00c09f52 \ No newline at end of file diff --git a/llvm/test/MC/Hexagon/inst_cmp_ugt.ll b/llvm/test/MC/Hexagon/inst_cmp_ugt.ll new file mode 100644 index 0000000..324a480 --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_cmp_ugt.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i1 @foo (i32 %a, i32 %b) +{ + %1 = icmp ugt i32 %a, %b + ret i1 %1 +} + +; CHECK: 0000 004160f2 00400000 00c09f52 \ No newline at end of file diff --git a/llvm/test/MC/Hexagon/inst_cmp_ult.ll b/llvm/test/MC/Hexagon/inst_cmp_ult.ll new file mode 100644 index 0000000..ca04167 --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_cmp_ult.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i1 @foo (i32 %a, i32 %b) +{ + %1 = icmp ult i32 %a, %b + ret i1 %1 +} + +; CHECK: 0000 004061f2 00400000 00c09f52 \ No newline at end of file -- 2.7.4