From 901489081989e0efadf790a6de387dbca271a0b6 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 30 Dec 2014 22:28:31 +0000 Subject: [PATCH] [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. llvm-svn: 225009 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 10 +- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 176 +++++++++++++------------- llvm/test/MC/Disassembler/Hexagon/nv_st.txt | 51 ++++++++ 3 files changed, 141 insertions(+), 96 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index da35791..4fe10f4 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -655,15 +655,15 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); case Hexagon::S2_storeri_io: - case Hexagon::STriw_nv_V4: + case Hexagon::S2_storerinew_io: return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); case Hexagon::S2_storerh_io: - case Hexagon::STrih_nv_V4: + case Hexagon::S2_storerhnew_io: return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); case Hexagon::S2_storerb_io: - case Hexagon::STrib_nv_V4: + case Hexagon::S2_storerbnew_io: return isUInt<6>(MI->getOperand(1).getImm()); case Hexagon::L2_loadrd_io: @@ -1556,10 +1556,10 @@ int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const { return Hexagon::STrih_shl_nv_V4; case Hexagon::STriw_f: - return Hexagon::STriw_nv_V4; + return Hexagon::S2_storerinew_io; case Hexagon::STriw_indexed_f: - return Hexagon::S2_storerinew_io; + return Hexagon::S4_storerinew_rr; case Hexagon::STriw_shl_V4: return Hexagon::STriw_shl_nv_V4; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 5ba8037..5509e18 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1210,113 +1210,107 @@ let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in { u6_2Ext, 0b10>, AddrModeRel; } -// multiclass for new-value store instructions with base + immediate offset. -// and MEMri operand. -multiclass ST_MEMri_Pbase_nv { - let isPredicatedNew = isPredNew in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins PredRegs:$src1, MEMri:$addr, RC: $src2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($addr) = $src2.new", - []>, - Requires<[HasV4T]>; -} - -multiclass ST_MEMri_Pred_nv { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_MEMri_Pbase_nv; +//===----------------------------------------------------------------------===// +// Template class for non-predicated post increment .new stores +// mem[bhwd](Rx++#s4:[0123])=Nt.new +//===----------------------------------------------------------------------===// +let isPredicable = 1, hasSideEffects = 0, validSubTargets = HasV4SubT, + addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 3 in +class T_StorePI_nv MajOp > + : NVInstPI_V4 <(outs IntRegs:$_dst_), + (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2), + mnemonic#"($src1++#$offset) = $src2.new", + [], "$src1 = $_dst_">, + AddrModeRel { + bits<5> src1; + bits<3> src2; + bits<7> offset; + bits<4> offsetBits; + + string ImmOpStr = !cast(ImmOp); + let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, + !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, + /* s4_0Imm */ offset{3-0})); + let IClass = 0b1010; - // Predicate new - defm _cdn#NAME : ST_MEMri_Pbase_nv; + let Inst{27-21} = 0b1011101; + let Inst{20-16} = src1; + let Inst{13} = 0b0; + let Inst{12-11} = MajOp; + let Inst{10-8} = src2; + let Inst{7} = 0b0; + let Inst{6-3} = offsetBits; + let Inst{1} = 0b0; } -} -let mayStore = 1, isNVStore = 1, isExtendable = 1, hasSideEffects = 0 in -multiclass ST_MEMri_nv ImmBits, bits<5> PredImmBits> { +//===----------------------------------------------------------------------===// +// Template class for predicated post increment .new stores +// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new +//===----------------------------------------------------------------------===// +let isPredicated = 1, hasSideEffects = 0, validSubTargets = HasV4SubT, + addrMode = PostInc, isNVStore = 1, isNewValue = 1, opNewValue = 4 in +class T_StorePI_nv_pred MajOp, bit isPredNot, bit isPredNew > + : NVInstPI_V4 <(outs IntRegs:$_dst_), + (ins PredRegs:$src1, IntRegs:$src2, + ImmOp:$offset, IntRegs:$src3), + !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", + ") ")#mnemonic#"($src2++#$offset) = $src3.new", + [], "$src2 = $_dst_">, + AddrModeRel { + bits<2> src1; + bits<5> src2; + bits<3> src3; + bits<7> offset; + bits<4> offsetBits; - let CextOpcode = CextOp, BaseOpcode = CextOp in { - let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits, - isPredicable = 1 in - def NAME#_nv_V4 : NVInst_V4<(outs), - (ins MEMri:$addr, RC:$src), - mnemonic#"($addr) = $src.new", - []>, - Requires<[HasV4T]>; + string ImmOpStr = !cast(ImmOp); + let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, + !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, + /* s4_0Imm */ offset{3-0})); + let isPredicatedNew = isPredNew; + let isPredicatedFalse = isPredNot; - let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits, - hasSideEffects = 0, isPredicated = 1 in { - defm Pt : ST_MEMri_Pred_nv; - defm NotPt : ST_MEMri_Pred_nv; - } - } -} + let IClass = 0b1010; -let addrMode = BaseImmOffset, isMEMri = "true", validSubTargets = HasV4SubT, -mayStore = 1 in { - let accessSize = ByteAccess in - defm STrib: ST_MEMri_nv<"memb", "STrib", IntRegs, 11, 6>, AddrModeRel; + let Inst{27-21} = 0b1011101; + let Inst{20-16} = src2; + let Inst{13} = 0b1; + let Inst{12-11} = MajOp; + let Inst{10-8} = src3; + let Inst{7} = isPredNew; + let Inst{6-3} = offsetBits; + let Inst{2} = isPredNot; + let Inst{1-0} = src1; + } - let accessSize = HalfWordAccess in - defm STrih: ST_MEMri_nv<"memh", "STrih", IntRegs, 12, 7>, AddrModeRel; +multiclass ST_PostInc_Pred_nv MajOp, bit PredNot> { + def _pi : T_StorePI_nv_pred ; - let accessSize = WordAccess in - defm STriw: ST_MEMri_nv<"memw", "STriw", IntRegs, 13, 8>, AddrModeRel; + // Predicate new + def new_pi : T_StorePI_nv_pred ; } -//===----------------------------------------------------------------------===// -// Post increment store -// mem[bhwd](Rx++#s4:[0123])=Nt.new -//===----------------------------------------------------------------------===// - -multiclass ST_PostInc_Pbase_nv { - let isPredicatedNew = isPredNew in - def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3.new", - [], - "$src2 = $dst">, - Requires<[HasV4T]>; -} +multiclass ST_PostInc_nv MajOp> { + let BaseOpcode = "POST_"#BaseOp in { + def S2_#NAME#_pi : T_StorePI_nv ; -multiclass ST_PostInc_Pred_nv { - let isPredicatedFalse = PredNot in { - defm _c#NAME : ST_PostInc_Pbase_nv; - // Predicate new - let Predicates = [HasV4T], validSubTargets = HasV4SubT in - defm _cdn#NAME : ST_PostInc_Pbase_nv; + // Predicated + defm S2_p#NAME#t : ST_PostInc_Pred_nv ; + defm S2_p#NAME#f : ST_PostInc_Pred_nv ; } } -let hasCtrlDep = 1, isNVStore = 1, hasSideEffects = 0 in -multiclass ST_PostInc_nv { +let accessSize = ByteAccess, isCodeGenOnly = 0 in +defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>; - let BaseOpcode = "POST_"#BaseOp in { - let isPredicable = 1 in - def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), - (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), - mnemonic#"($src1++#$offset) = $src2.new", - [], - "$src1 = $dst">, - Requires<[HasV4T]>; - - let isPredicated = 1 in { - defm Pt : ST_PostInc_Pred_nv; - defm NotPt : ST_PostInc_Pred_nv; - } - } -} +let accessSize = HalfWordAccess, isCodeGenOnly = 0 in +defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>; -let addrMode = PostInc, validSubTargets = HasV4SubT in { -defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel; -defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel; -defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel; -} +let accessSize = WordAccess, isCodeGenOnly = 0 in +defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>; // memb(Rx++#s4:0:circ(Mu))=Nt.new // memb(Rx++I:circ(Mu))=Nt.new diff --git a/llvm/test/MC/Disassembler/Hexagon/nv_st.txt b/llvm/test/MC/Disassembler/Hexagon/nv_st.txt index 75724f6..f9e97b5 100644 --- a/llvm/test/MC/Disassembler/Hexagon/nv_st.txt +++ b/llvm/test/MC/Disassembler/Hexagon/nv_st.txt @@ -6,6 +6,9 @@ 0x1f 0x40 0x7f 0x70 0x15 0xc2 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memb(r17+#21) = r2.new +0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: memb(r17++#5) = r2.new 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new @@ -34,6 +37,20 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memb(r17+#21) = r2.new +0x1f 0x40 0x7f 0x70 0x2b 0xe2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memb(r17++#5) = r2.new +0x1f 0x40 0x7f 0x70 0x2f 0xe2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memb(r17++#5) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xe2 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memb(r17++#5) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xe2 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r2.new 0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b # CHECK: r31 = r31 @@ -41,6 +58,9 @@ 0x1f 0x40 0x7f 0x70 0x15 0xca 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memh(r17+#42) = r2.new +0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: memh(r17++#10) = r2.new 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new @@ -69,6 +89,20 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memh(r17+#42) = r2.new +0x1f 0x40 0x7f 0x70 0x2b 0xea 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memh(r17++#10) = r2.new +0x1f 0x40 0x7f 0x70 0x2f 0xea 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memh(r17++#10) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xea 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memh(r17++#10) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xea 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r2.new 0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b # CHECK: r31 = r31 @@ -76,6 +110,9 @@ 0x1f 0x40 0x7f 0x70 0x15 0xd2 0xb1 0xa1 # CHECK: r31 = r31 # CHECK-NEXT: memw(r17+#84) = r2.new +0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: memw(r17++#20) = r2.new 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 # CHECK: r31 = r31 # CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new @@ -104,3 +141,17 @@ # CHECK: p3 = r5 # CHECK-NEXT: r31 = r31 # CHECK-NEXT: if (!p3.new) memw(r17+#84) = r2.new +0x1f 0x40 0x7f 0x70 0x2b 0xf2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (p3) memw(r17++#20) = r2.new +0x1f 0x40 0x7f 0x70 0x2f 0xf2 0xb1 0xab +# CHECK: r31 = r31 +# CHECK-NEXT: if (!p3) memw(r17++#20) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xab 0xf2 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (p3.new) memw(r17++#20) = r2.new +0x03 0x40 0x45 0x85 0x1f 0x40 0x7f 0x70 0xaf 0xf2 0xb1 0xab +# CHECK: p3 = r5 +# CHECK-NEXT: r31 = r31 +# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r2.new -- 2.7.4