From 9004444d815579e01c393553f598ffbe9da4564b Mon Sep 17 00:00:00 2001 From: Stefan Pintilie Date: Fri, 16 Nov 2018 19:24:23 +0000 Subject: [PATCH] Revert "[PowerPC] Make no-PIC default to match GCC - LLVM" This reverts commit r347069 llvm-svn: 347076 --- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 6 ++- .../CodeGen/PowerPC/MCSE-caller-preserved-reg.ll | 2 +- llvm/test/CodeGen/PowerPC/addegluecrash.ll | 1 - llvm/test/CodeGen/PowerPC/atomics-constant.ll | 6 +-- llvm/test/CodeGen/PowerPC/f128-aggregates.ll | 4 +- llvm/test/CodeGen/PowerPC/f128-conv.ll | 2 +- llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll | 2 +- llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll | 2 +- llvm/test/CodeGen/PowerPC/fast-isel-call.ll | 2 +- llvm/test/CodeGen/PowerPC/func-addr-consts.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-13.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-6.ll | 4 +- .../PowerPC/p8-scalar_vector_conversions.ll | 4 +- llvm/test/CodeGen/PowerPC/ppc64-blnop.ll | 12 ++--- llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll | 18 +++---- llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll | 6 +-- llvm/test/CodeGen/PowerPC/ppcf128-endian.ll | 2 +- llvm/test/CodeGen/PowerPC/pr32140.ll | 15 ++---- llvm/test/CodeGen/PowerPC/preemption.ll | 3 +- llvm/test/CodeGen/PowerPC/save-bp.ll | 4 +- llvm/test/CodeGen/PowerPC/sjlj_no0x.ll | 6 +-- llvm/test/CodeGen/PowerPC/swaps-le-6.ll | 6 +-- llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesieqsc.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesieqsi.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesieqsll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesieqss.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesiequc.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesiequi.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesiequll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesiequs.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesigesc.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesigesi.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesigesll.ll | 28 +++++----- llvm/test/CodeGen/PowerPC/testComparesigess.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesigtsc.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtsi.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtsll.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtss.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtuc.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtui.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesigtus.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesilesc.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesilesi.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesilesll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesiless.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesinesc.ll | 62 +++++++++------------- llvm/test/CodeGen/PowerPC/testComparesinesi.ll | 62 +++++++++------------- llvm/test/CodeGen/PowerPC/testComparesinesll.ll | 24 +++++---- llvm/test/CodeGen/PowerPC/testComparesiness.ll | 62 +++++++++------------- llvm/test/CodeGen/PowerPC/testComparesineuc.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesineui.ll | 62 +++++++++------------- llvm/test/CodeGen/PowerPC/testComparesineull.ll | 24 +++++---- llvm/test/CodeGen/PowerPC/testComparesineus.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testCompareslleqss.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllequc.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllequi.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllequll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllequs.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllgesc.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesllgesi.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesllgesll.ll | 28 +++++----- llvm/test/CodeGen/PowerPC/testComparesllgess.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesllgtui.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesllgtus.ll | 4 +- llvm/test/CodeGen/PowerPC/testCompareslllesc.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testCompareslllesi.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testCompareslllesll.ll | 20 ++++--- llvm/test/CodeGen/PowerPC/testComparesllless.ll | 10 ++-- llvm/test/CodeGen/PowerPC/testComparesllltui.ll | 4 +- llvm/test/CodeGen/PowerPC/testComparesllnesll.ll | 24 +++++---- llvm/test/CodeGen/PowerPC/testComparesllneull.ll | 24 +++++---- llvm/test/CodeGen/PowerPC/toc-float.ll | 4 +- llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll | 4 +- llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll | 2 +- 81 files changed, 585 insertions(+), 516 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index d7eb915..3441039 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -214,7 +214,11 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, if (TT.isOSDarwin()) return Reloc::DynamicNoPIC; - // Otherwise is static by default. + // Non-darwin 64-bit platforms are PIC by default. + if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) + return Reloc::PIC_; + + // 32-bit is static by default. return Reloc::Static; } diff --git a/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll b/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll index 38b7d51..fa5916a 100644 --- a/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll +++ b/llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; The instructions addis,addi, bl are used to calculate the address of TLS ; thread local variables. These TLS access code sequences are generated ; repeatedly every time the thread local variable is accessed. By communicating diff --git a/llvm/test/CodeGen/PowerPC/addegluecrash.ll b/llvm/test/CodeGen/PowerPC/addegluecrash.ll index a765373..a1d9805 100644 --- a/llvm/test/CodeGen/PowerPC/addegluecrash.ll +++ b/llvm/test/CodeGen/PowerPC/addegluecrash.ll @@ -27,7 +27,6 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n ; CHECK-NEXT: mr 4, 10 ; CHECK-NEXT: clrldi 4, 4, 32 ; CHECK-NEXT: std 4, 0(3) -; CHECK-NEXT: std 6, -8(1) # 8-byte Folded Spill ; CHECK-NEXT: blr %1 = load i64, i64* %a, align 8 %conv = zext i64 %1 to i128 diff --git a/llvm/test/CodeGen/PowerPC/atomics-constant.ll b/llvm/test/CodeGen/PowerPC/atomics-constant.ll index ac0b16b..559cd9e 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-constant.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-constant.ll @@ -8,14 +8,14 @@ target triple = "powerpc64le-unknown-linux-gnu" define i64 @foo() { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, a@toc@ha +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: addi 3, 3, a@toc@l +; CHECK-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-NEXT: cmpd 7, 4, 4 ; CHECK-NEXT: ld 3, 0(3) -; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: bne- 7, .+4 ; CHECK-NEXT: isync +; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: blr entry: %value = load atomic i64, i64* @a acquire, align 8 diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll index d671c76..8c934ba 100644 --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -verify-machineinstrs \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \ ; RUN: | FileCheck -check-prefix=CHECK-BE %s diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll index ef433bd..6c8d596 100644 --- a/llvm/test/CodeGen/PowerPC/f128-conv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \ ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll index d346683..d5ffea6 100644 --- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -verify-machineinstrs -enable-ppc-quad-precision \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll index bae676c..3ab5ee9 100644 --- a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll +++ b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ -; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \ +; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -enable-ppc-quad-precision < %s | FileCheck %s ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \ diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll index 8823beb..a080bae 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll @@ -2,7 +2,7 @@ ; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; When fastisel better supports VSX fix up this test case. ; -; RUN: llc < %s -O0 -relocation-model=pic -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 define i32 @t1(i8 signext %a) nounwind { %1 = sext i8 %a to i32 diff --git a/llvm/test/CodeGen/PowerPC/func-addr-consts.ll b/llvm/test/CodeGen/PowerPC/func-addr-consts.ll index 938b1bd..fe2bd7f 100644 --- a/llvm/test/CodeGen/PowerPC/func-addr-consts.ll +++ b/llvm/test/CodeGen/PowerPC/func-addr-consts.ll @@ -12,5 +12,5 @@ entry: ret void } -; CHECK: .section gsection,"a",@progbits -; CHECK: .section hsection,"a",@progbits +; CHECK: .section gsection,"aw",@progbits +; CHECK: .section hsection,"aw",@progbits diff --git a/llvm/test/CodeGen/PowerPC/mcm-13.ll b/llvm/test/CodeGen/PowerPC/mcm-13.ll index d7c50ef..6f69b43 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-13.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-13.ll @@ -1,5 +1,5 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s ; Test correct code generation for medium and large code model ; for loading and storing a weak variable diff --git a/llvm/test/CodeGen/PowerPC/mcm-6.ll b/llvm/test/CodeGen/PowerPC/mcm-6.ll index a8fe9c3..b1ad8c2 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-6.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-6.ll @@ -1,5 +1,5 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s ; Test correct code generation for medium and large code model ; for loading and storing a tentatively defined variable. diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index 1b11bfd..12585c2 100644 --- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ ; RUN: | FileCheck %s ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ ; RUN: | FileCheck %s -check-prefix=CHECK-LE ; The build[csilf] functions simply test the scalar_to_vector handling with diff --git a/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll b/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll index 6c3b55d..3b3d9ad 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-blnop.ll @@ -1,11 +1,11 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS +; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS ; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -relocation-model=pic -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS -; RUN: llc < %s -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc < %s -function-sections -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-FS +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -code-model=small -mcpu=pwr8 | FileCheck %s -check-prefix=SCM %class.T = type { [2 x i8] } diff --git a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll index 2593fa4..f5319b2 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll @@ -1,33 +1,33 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-LE \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-BE -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-BE-NOVSX -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-vsx < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-LE-NOVSX --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-P9 --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-vsx < %s | FileCheck %s -check-prefix=CHECK-NOVSX \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-power9-vector -mattr=-direct-move < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-LE --implicit-check-not xxswapd diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll index 3819e26..a352505 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,8 +1,8 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr8 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr8 \ ; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s -; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mattr=+altivec \ +; RUN: llc -verify-machineinstrs < %s -mattr=+altivec \ ; RUN: -mattr=-vsx | FileCheck %s -; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mcpu=pwr9 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 \ ; RUN: -mattr=-direct-move -mattr=+altivec | FileCheck %s ; Currently VSX support is disabled for this test because we generate lxsdx diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll index 851942c..738577a 100644 --- a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/pr32140.ll b/llvm/test/CodeGen/PowerPC/pr32140.ll index 7d95a6e..3feb9bd 100644 --- a/llvm/test/CodeGen/PowerPC/pr32140.ll +++ b/llvm/test/CodeGen/PowerPC/pr32140.ll @@ -10,10 +10,7 @@ define void @bswapStorei64Toi32() { ; CHECK-LABEL: bswapStorei64Toi32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, ai@toc@ha -; CHECK-NEXT: addis 4, 2, bi@toc@ha -; CHECK-NEXT: lwa 3, ai@toc@l(3) -; CHECK-NEXT: addi 4, 4, bi@toc@l +; CHECK: lwa 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 32, 32 ; CHECK-NEXT: stwbrx 3, 0, 4 ; CHECK-NEXT: blr @@ -29,10 +26,7 @@ entry: define void @bswapStorei32Toi16() { ; CHECK-LABEL: bswapStorei32Toi16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, as@toc@ha -; CHECK-NEXT: addis 4, 2, bs@toc@ha -; CHECK-NEXT: lha 3, as@toc@l(3) -; CHECK-NEXT: addi 4, 4, bs@toc@l +; CHECK: lha 3, 0(3) ; CHECK-NEXT: srwi 3, 3, 16 ; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: blr @@ -48,10 +42,7 @@ entry: define void @bswapStorei64Toi16() { ; CHECK-LABEL: bswapStorei64Toi16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addis 3, 2, as@toc@ha -; CHECK-NEXT: addis 4, 2, bs@toc@ha -; CHECK-NEXT: lha 3, as@toc@l(3) -; CHECK-NEXT: addi 4, 4, bs@toc@l +; CHECK: lha 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 16, 48 ; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/preemption.ll b/llvm/test/CodeGen/PowerPC/preemption.ll index 9a0d81f..5652f6d 100644 --- a/llvm/test/CodeGen/PowerPC/preemption.ll +++ b/llvm/test/CodeGen/PowerPC/preemption.ll @@ -1,5 +1,4 @@ -; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ -; RUN: < %s | FileCheck %s +; RUN: llc -mtriple powerpc64le-unkown-gnu-linux < %s | FileCheck %s ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=static \ ; RUN: < %s | FileCheck --check-prefix=STATIC %s ; RUN: llc -mtriple powerpc64le-unkown-gnu-linux -relocation-model=pic \ diff --git a/llvm/test/CodeGen/PowerPC/save-bp.ll b/llvm/test/CodeGen/PowerPC/save-bp.ll index 8a7cef6..2e403cb 100644 --- a/llvm/test/CodeGen/PowerPC/save-bp.ll +++ b/llvm/test/CodeGen/PowerPC/save-bp.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=ppc64-- -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64 -; RUN: llc -ppc-always-use-base-pointer -relocation-model=static < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 -; RUN: llc -ppc-always-use-base-pointer -relocation-model=pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC +; RUN: llc -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32 +; RUN: llc -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC ; CHECK-LABEL: fred: diff --git a/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll b/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll index 01053c4..2018bcb 100644 --- a/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll +++ b/llvm/test/CodeGen/PowerPC/sjlj_no0x.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll index 0811287..ac0bcc7 100644 --- a/llvm/test/CodeGen/PowerPC/swaps-le-6.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-6.ll @@ -1,13 +1,13 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ ; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -O3 < %s | FileCheck %s -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ ; RUN: --implicit-check-not xxswapd -; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -mattr=-power9-vector < %s | FileCheck %s diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll index 62d66c5..4341b59 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll index 2b9d0ef..9623a63 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll index 76958d7..513caa3 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsc.ll @@ -69,11 +69,12 @@ entry: define void @test_ieqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_ieqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_ieqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll index cf9bc4e..97fd744 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsi.ll @@ -69,11 +69,12 @@ entry: define void @test_ieqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_ieqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_ieqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll index 4a861f0..bb0d6ca 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll @@ -67,11 +67,12 @@ entry: define void @test_ieqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -84,11 +85,12 @@ entry: define void @test_ieqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -101,10 +103,11 @@ entry: define void @test_ieqsll_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 @@ -117,10 +120,11 @@ entry: define void @test_ieqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll index f2413bf..24cee5a 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesieqss.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesieqss.ll @@ -69,11 +69,12 @@ entry: define void @test_ieqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_ieqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_ieqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll index ae2cff9..4ce9747 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequc.ll @@ -69,11 +69,12 @@ entry: define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_iequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_iequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll index 3988881..a0dc890 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequi.ll @@ -69,11 +69,12 @@ entry: define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_iequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_iequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll index ba96d4b..60e11e6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll @@ -67,11 +67,12 @@ entry: define void @test_iequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -84,11 +85,12 @@ entry: define void @test_iequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -101,10 +103,11 @@ entry: define void @test_iequll_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 @@ -117,10 +120,11 @@ entry: define void @test_iequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll index 3816d2b..710eaf5 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiequs.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiequs.ll @@ -69,11 +69,12 @@ entry: define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_iequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_iequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll index 5e1d576..80152f8 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll @@ -36,11 +36,12 @@ entry: define void @test_igesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i8 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i8 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll index 509b05c..d5a194e 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll @@ -36,11 +36,12 @@ entry: define void @test_igesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i32 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i32 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll index ecfe5b7..0926d9e 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll @@ -1,10 +1,10 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define signext i32 @test_igesll(i64 %a, i64 %b) { @@ -63,12 +63,11 @@ entry: define void @test_igesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: subfc r3, r4, r3 -; CHECK-NEXT: rldicl r3, r4, 1, 63 -; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3 ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -81,12 +80,13 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -98,10 +98,11 @@ entry: define void @test_igesll_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 @@ -113,10 +114,11 @@ entry: define void @test_igesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 diff --git a/llvm/test/CodeGen/PowerPC/testComparesigess.ll b/llvm/test/CodeGen/PowerPC/testComparesigess.ll index b20838f..8dcdafb 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigess.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigess.ll @@ -36,11 +36,12 @@ entry: define void @test_igess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i16 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i16 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll index c669d69..8009043 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll index 9b5f1f4..77dfc35 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll index c2198d1..75314d7 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll index 93e6ccd..23ddbe3 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll index 2886130..540b820 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll index a81a1a6..6fef78c 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll index 7beca85..07e8101 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll index 9c128fb..c625dca 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll @@ -36,11 +36,12 @@ entry: define void @test_ilesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i8 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i8 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll index 40aa1e73..343aa51 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll @@ -36,11 +36,12 @@ entry: define void @test_ilesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i32 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i32 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll index f1e0629..bd51ad6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll @@ -65,12 +65,13 @@ entry: define void @test_ilesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r5) ; CHECK-NEXT: blr entry: %cmp = icmp sle i64 %a, %b @@ -83,12 +84,13 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i64 %a, %b @@ -100,11 +102,12 @@ entry: define void @test_ilesll_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 @@ -116,11 +119,12 @@ entry: define void @test_ilesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiless.ll b/llvm/test/CodeGen/PowerPC/testComparesiless.ll index 526fd7f..10e7b39 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiless.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiless.ll @@ -36,11 +36,12 @@ entry: define void @test_iless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i16 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i16 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll index 6f7bb3c..a498f64 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesc.ll @@ -1,17 +1,16 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_inesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,8 +23,7 @@ entry: define signext i32 @test_inesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_sext: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -39,8 +37,7 @@ entry: define signext i32 @test_inesc_z(i8 signext %a) { ; CHECK-LABEL: test_inesc_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -52,8 +49,7 @@ entry: define signext i32 @test_inesc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_inesc_sext_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 @@ -66,13 +62,11 @@ entry: define void @test_inesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, %b @@ -83,14 +77,12 @@ entry: define void @test_inesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_inesc_sext_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, %b @@ -101,12 +93,10 @@ entry: define void @test_inesc_z_store(i8 signext %a) { ; CHECK-LABEL: test_inesc_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 @@ -117,13 +107,11 @@ entry: define void @test_inesc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_inesc_sext_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll index 006627f..b47f6c8 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesi.ll @@ -1,17 +1,16 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_inesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,8 +23,7 @@ entry: define signext i32 @test_inesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_sext: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -39,8 +37,7 @@ entry: define signext i32 @test_inesi_z(i32 signext %a) { ; CHECK-LABEL: test_inesi_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -52,8 +49,7 @@ entry: define signext i32 @test_inesi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_inesi_sext_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 @@ -66,13 +62,11 @@ entry: define void @test_inesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, %b @@ -83,14 +77,12 @@ entry: define void @test_inesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_inesi_sext_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, %b @@ -101,12 +93,10 @@ entry: define void @test_inesi_z_store(i32 signext %a) { ; CHECK-LABEL: test_inesi_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 @@ -117,13 +107,11 @@ entry: define void @test_inesi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_inesi_sext_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll index f8dd051..33416a0 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesinesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesinesll.ll @@ -61,11 +61,12 @@ entry: define void @test_inesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -77,11 +78,12 @@ entry: define void @test_inesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -93,10 +95,11 @@ entry: define void @test_inesll_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 @@ -108,10 +111,11 @@ entry: define void @test_inesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesiness.ll b/llvm/test/CodeGen/PowerPC/testComparesiness.ll index 5fa96f3..66c95cd 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesiness.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesiness.ll @@ -1,17 +1,16 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define signext i32 @test_iness(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,8 +23,7 @@ entry: define signext i32 @test_iness_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_sext: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -39,8 +37,7 @@ entry: define signext i32 @test_iness_z(i16 signext %a) { ; CHECK-LABEL: test_iness_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -52,8 +49,7 @@ entry: define signext i32 @test_iness_sext_z(i16 signext %a) { ; CHECK-LABEL: test_iness_sext_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 @@ -66,13 +62,11 @@ entry: define void @test_iness_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, %b @@ -83,14 +77,12 @@ entry: define void @test_iness_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iness_sext_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, %b @@ -101,12 +93,10 @@ entry: define void @test_iness_z_store(i16 signext %a) { ; CHECK-LABEL: test_iness_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 @@ -117,13 +107,11 @@ entry: define void @test_iness_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_iness_sext_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll index 4f65197..fe91449 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineuc.ll @@ -66,12 +66,13 @@ entry: define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, %b @@ -84,12 +85,13 @@ define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, %b @@ -101,11 +103,12 @@ entry: define void @test_ineuc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 @@ -117,12 +120,13 @@ entry: define void @test_ineuc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineui.ll b/llvm/test/CodeGen/PowerPC/testComparesineui.ll index a8c61b9..ef12627 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineui.ll @@ -1,17 +1,16 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_ineui(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,8 +23,7 @@ entry: define signext i32 @test_ineui_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_sext: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 +; CHECK: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -39,8 +37,7 @@ entry: define signext i32 @test_ineui_z(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -52,8 +49,7 @@ entry: define signext i32 @test_ineui_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_sext_z: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 +; CHECK: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 @@ -66,13 +62,11 @@ entry: define void @test_ineui_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, %b @@ -83,14 +77,12 @@ entry: define void @test_ineui_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_ineui_sext_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK: xor r3, r3, r4 +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, %b @@ -101,12 +93,10 @@ entry: define void @test_ineui_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 @@ -117,13 +107,11 @@ entry: define void @test_ineui_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_ineui_sext_z_store: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha -; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK: cntlzw r3, r3 +; CHECK: srwi r3, r3, 5 +; CHECK: xori r3, r3, 1 +; CHECK: neg r3, r3 +; CHECK: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineull.ll b/llvm/test/CodeGen/PowerPC/testComparesineull.ll index 9c5a137..7f80de4 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineull.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineull.ll @@ -61,11 +61,12 @@ entry: define void @test_ineull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -77,11 +78,12 @@ entry: define void @test_ineull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -93,10 +95,11 @@ entry: define void @test_ineull_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 @@ -108,10 +111,11 @@ entry: define void @test_ineull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesineus.ll b/llvm/test/CodeGen/PowerPC/testComparesineus.ll index 7e6ee9f..9efd5d6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesineus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesineus.ll @@ -67,12 +67,13 @@ entry: define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, %b @@ -85,12 +86,13 @@ define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, %b @@ -102,11 +104,12 @@ entry: define void @test_ineus_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 @@ -118,12 +121,13 @@ entry: define void @test_ineus_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll index eb55ed0..bdd4568 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll @@ -69,11 +69,12 @@ entry: define void @test_lleqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -86,12 +87,13 @@ entry: define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -104,10 +106,11 @@ entry: define void @test_lleqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -120,11 +123,12 @@ entry: define void @test_lleqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll index dfb61bf..6d879c6 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsi.ll @@ -68,11 +68,12 @@ entry: define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -85,12 +86,13 @@ entry: define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -103,10 +105,11 @@ entry: define void @test_lleqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr ; CHECKNEXT: blr entry: @@ -120,11 +123,12 @@ entry: define void @test_lleqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll index 9368d28..f997bd9 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll @@ -66,11 +66,12 @@ entry: define void @test_lleqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -83,11 +84,12 @@ entry: define void @test_lleqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -100,10 +102,11 @@ entry: define void @test_lleqsll_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 @@ -116,10 +119,11 @@ entry: define void @test_lleqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll index 8f222a8..0c4edc3 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslleqss.ll @@ -68,11 +68,12 @@ entry: define void @test_lleqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -85,12 +86,13 @@ entry: define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -103,10 +105,11 @@ entry: define void @test_lleqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -119,11 +122,12 @@ entry: define void @test_lleqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll index 294ebdc..85523f0 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequc.ll @@ -68,11 +68,12 @@ entry: define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -85,12 +86,13 @@ entry: define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -103,10 +105,11 @@ entry: define void @test_llequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -119,11 +122,12 @@ entry: define void @test_llequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stb r3, glob@toc@l(r4) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll index d61591b..cb7be18 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequi.ll @@ -68,11 +68,12 @@ entry: define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -85,12 +86,13 @@ entry: define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -103,10 +105,11 @@ entry: define void @test_llequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -119,11 +122,12 @@ entry: define void @test_llequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: stw r3, glob@toc@l(r4) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll index 5cb6793..01136f1 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll @@ -66,11 +66,12 @@ entry: define void @test_llequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -83,11 +84,12 @@ entry: define void @test_llequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, %b @@ -100,10 +102,11 @@ entry: define void @test_llequll_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 58, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 @@ -116,10 +119,11 @@ entry: define void @test_llequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll index 937d95d..459df8b 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllequs.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllequs.ll @@ -68,11 +68,12 @@ entry: define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -85,12 +86,13 @@ entry: define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -103,10 +105,11 @@ entry: define void @test_llequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -119,11 +122,12 @@ entry: define void @test_llequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: sth r3, glob@toc@l(r4) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll index 75a9191..39499a6 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll @@ -36,11 +36,12 @@ entry: define void @test_llgesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i8 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i8 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll index c1b5161..d020000 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll @@ -36,11 +36,12 @@ entry: define void @test_llgesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i32 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i32 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll index 1981600..f2096c2 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll @@ -1,10 +1,10 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define i64 @test_llgesll(i64 %a, i64 %b) { @@ -63,12 +63,11 @@ entry: define void @test_llgesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_store: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: subfc r3, r4, r3 -; CHECK-NEXT: rldicl r3, r4, 1, 63 -; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK: sradi r6, r3, 63 +; CHECK: subfc r3, r4, r3 +; CHECK: rldicl r3, r4, 1, 63 +; CHECK: adde r3, r6, r3 +; CHECK: std r3, ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -81,12 +80,13 @@ define void @test_llgesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: rldicl r3, r4, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i64 %a, %b @@ -98,10 +98,11 @@ entry: define void @test_llgesll_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 @@ -113,10 +114,11 @@ entry: define void @test_llgesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: not r3, r3 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sgt i64 %a, -1 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll index b5765aa..71af3d3 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll @@ -36,11 +36,12 @@ entry: define void @test_llgess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i16 %a, %b @@ -52,11 +53,12 @@ entry: define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sge i16 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll index deb9ad5..0dc1374 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll index 685026a..ba70713 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll index a1c8777..d07e859 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll index 94bb145..3758e8e 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll index d112757..575451e 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll @@ -37,11 +37,12 @@ entry: define void @test_lllesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i8 %a, %b @@ -53,11 +54,12 @@ entry: define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stb r3, glob@toc@l(r5) +; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i8 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll index 9c7608e..e04641d 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll @@ -37,11 +37,12 @@ entry: define void @test_lllesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i32 %a, %b @@ -53,11 +54,12 @@ entry: define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: stw r3, glob@toc@l(r5) +; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i32 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll index ff0f142..b5c340d 100644 --- a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll +++ b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll @@ -70,12 +70,13 @@ entry: define void @test_lllesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: adde r3, r6, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r5) ; CHECK-NEXT: blr entry: %cmp = icmp sle i64 %a, %b @@ -89,12 +90,13 @@ define void @test_lllesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_sext_store: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r4, 63 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: neg r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i64 %a, %b @@ -107,11 +109,12 @@ entry: define void @test_lllesll_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 @@ -124,11 +127,12 @@ entry: define void @test_lllesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: or r3, r5, r3 ; CHECK-NEXT: sradi r3, r3, 63 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp slt i64 %a, 1 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllless.ll b/llvm/test/CodeGen/PowerPC/testComparesllless.ll index 6750da6..1f06652 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllless.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllless.ll @@ -37,11 +37,12 @@ entry: define void @test_llless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i16 %a, %b @@ -53,11 +54,12 @@ entry: define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 -; CHECK-NEXT: sth r3, glob@toc@l(r5) +; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp sle i16 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll index 126d110..e785942b 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll @@ -1,7 +1,7 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl diff --git a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll index a037441..47545e9 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllnesll.ll @@ -61,11 +61,12 @@ entry: define void @test_llnesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -77,11 +78,12 @@ entry: define void @test_llnesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -93,10 +95,11 @@ entry: define void @test_llnesll_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 @@ -108,10 +111,11 @@ entry: define void @test_llnesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll index 7cd8747..b2c5086 100644 --- a/llvm/test/CodeGen/PowerPC/testComparesllneull.ll +++ b/llvm/test/CodeGen/PowerPC/testComparesllneull.ll @@ -61,11 +61,12 @@ entry: define void @test_llneull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) +; CHECK-NEXT: addic r5, r3, -1 +; CHECK-NEXT: subfe r3, r5, r3 +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -77,11 +78,12 @@ entry: define void @test_llneull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_sext_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addis r5, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r5) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, %b @@ -93,10 +95,11 @@ entry: define void @test_llneull_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 @@ -108,10 +111,11 @@ entry: define void @test_llneull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_sext_z_store: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: addis r4, r2, glob@toc@ha +; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, glob@toc@l(r4) +; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: blr entry: %cmp = icmp ne i64 %a, 0 diff --git a/llvm/test/CodeGen/PowerPC/toc-float.ll b/llvm/test/CodeGen/PowerPC/toc-float.ll index ff892e0..4f5c341 100644 --- a/llvm/test/CodeGen/PowerPC/toc-float.ll +++ b/llvm/test/CodeGen/PowerPC/toc-float.ll @@ -1,5 +1,5 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s -; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 <%s | FileCheck -check-prefix=CHECK-P9 %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 <%s | FileCheck -check-prefix=CHECK-P8 %s ; As the constant could be represented as float, a float is ; loaded from constant pool. diff --git a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll index d09b214..4d45e6e 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll @@ -1,6 +1,6 @@ -; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s -; RUN: llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr8 -mattr=-direct-move | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P9 diff --git a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll index 90a928a..e8fe9db 100644 --- a/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll +++ b/llvm/test/CodeGen/PowerPC/xray-tail-call-sled.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=asm -relocation-model=pic -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" { ; CHECK-LABEL: .Ltmp0: -- 2.7.4