From 8fdc35358dc2e5961d221c9445e04520bb5f0a72 Mon Sep 17 00:00:00 2001 From: "Kim, HeungJun" Date: Tue, 26 May 2009 14:15:40 +0900 Subject: [PATCH] [S5PC100] --- cpu/arm_cortexa8/s5pc100/cpu_init.S | 19 ++++++++++++++----- cpu/arm_cortexa8/s5pc100/interrupts.c | 20 +++++++++++--------- cpu/arm_cortexa8/s5pc100/speed.c | 4 ++++ include/s5pc1xx.h | 8 +++++--- 4 files changed, 34 insertions(+), 17 deletions(-) diff --git a/cpu/arm_cortexa8/s5pc100/cpu_init.S b/cpu/arm_cortexa8/s5pc100/cpu_init.S index af88d8e..3f32156 100644 --- a/cpu/arm_cortexa8/s5pc100/cpu_init.S +++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S @@ -1,8 +1,12 @@ /* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 + * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx * * Copyright (C) 2008 * Guennadi Liakhovetki, DENX Software Engineering, + + * Copyright (C) 2009 + * Inki Dae, SAMSUNG Electronics, + * Heungjun Kim, SAMSUNG Electronics, * * See file CREDITS for list of people who contributed to this * project. @@ -24,7 +28,6 @@ */ #include -/*#include */ #include .globl mem_ctrl_asm_init @@ -67,7 +70,10 @@ mem_ctrl_asm_init: ldr r1, =0xff001010 str r1, [r0] - /* BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh, force precharge, dynamic power down off */ + /* + * BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh, + * force precharge, dynamic power down off + */ ldr r0, =S5P_MEMCONTROL @ 0xe6000004 ldr r1, =0x00212100 str r1, [r0] @@ -85,8 +91,11 @@ mem_ctrl_asm_init: ldr r1, =0x20000000 str r1, [r0] - /* 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E), - * 100MHz%LE %LONG780(0x30C), 20MHz%LE %LONG156(0x9C), 10MHz%LE %LONG78(0x4E) + /* + * 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E), + * 100MHz%LE %LONG780(0x30C), + * 20MHz%LE %LONG156(0x9C), + * 10MHz%LE %LONG78(0x4E) */ ldr r0, =S5P_TIMINGAREF @ 0xe6000030 ldr r1, =0x0000050e diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c b/cpu/arm_cortexa8/s5pc100/interrupts.c index a2e1569..2eed8d9 100644 --- a/cpu/arm_cortexa8/s5pc100/interrupts.c +++ b/cpu/arm_cortexa8/s5pc100/interrupts.c @@ -19,6 +19,10 @@ * (C) Copyright 2008 * Guennadi Liakhovetki, DENX Software Engineering, * + * (C) Copyright 2009 + * Heungjun Kim, SAMSUNG Electronics, + * Inki Dae, SAMSUNG Electronics, + * * See file CREDITS for list of people who contributed to this * project. * @@ -39,9 +43,7 @@ */ #include -#include #include -#include #define PRESCALER_0 (16 - 1) /* prescaler of PWM timer 4 */ #define MUX4_DIV_12 (2 - 1) /* MUX 4, 1/2 period */ @@ -122,20 +124,20 @@ void udelay(unsigned long usec) { ulong tmo, tmp; - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ + tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ + } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; tmo /= (1000 * 1000); } - tmp = get_timer(0); /* get current timestamp */ + tmp = get_timer(0); /* get current timestamp */ if ((tmo + tmp + 1) < tmp) { /* if setting this fordward will roll time stamp */ - reset_timer_masked(); /* reset "advancing" timestamp to 0, set lastdec value */ + reset_timer_masked(); /* reset "advancing" timestamp to 0, set lastdec value */ } else { tmo += tmp; /* else, set advancing stamp wake up time */ } @@ -156,7 +158,7 @@ ulong get_timer_masked(void) ulong now = READ_TIMER(); if (lastdec >= now) { - timestamp += lastdec - now; /* normal mode */ + timestamp += lastdec - now; /* normal mode */ } else { timestamp += lastdec + count_value - now; /* overflow */ } diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c index 2b53ee0..fdd95e3 100644 --- a/cpu/arm_cortexa8/s5pc100/speed.c +++ b/cpu/arm_cortexa8/s5pc100/speed.c @@ -5,6 +5,10 @@ * (C) Copyright 2002 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * + * (C) Copyright 2009 + * Inki Dae, SAMSUNG Electronics, + * Heungjun Kim, SAMSUNG Electronics, + * * See file CREDITS for list of people who contributed to this * project. * diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h index 19ec182..aad23ed 100644 --- a/include/s5pc1xx.h +++ b/include/s5pc1xx.h @@ -40,7 +40,7 @@ #define S5P_PA_TZIC2 S5P_ADDR(0x05200000) /* TrustZone Interrupt Controller 2 */ #define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */ #define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */ -#define S5P_PA_ONENANDC S5P_ADDR(0x07100000) /* OneNand Controller */ +#define S5P_PA_ONENANDC S5P_ADDR(0x07100000) /* OneNAND Controller */ #define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */ #define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */ #define S5P_PA_SYSTEM S5P_ADDR(0x0a100000) /* System Timer */ @@ -1174,7 +1174,7 @@ #define S5P_TZIC2PCELLID3 S5P_TZIC2_BASE(PCELLID3_OFFSET + 0x0) /* - * Memory : SDRAM, SROM, OneNand + * Memory : SDRAM, SROM, OneNAND */ /* DRAM Memory Controller */ @@ -1289,9 +1289,10 @@ #define S5P_SROM_BC4_REG __REG(S5P_SROM_BC4) #define S5P_SROM_BC5_REG __REG(S5P_SROM_BC5) -/* OneNand */ +/* OneNAND */ #define S5P_ONENANDC_BASE(x) (S5P_PA_ONENANDC + (x)) +/* OneNAND offset */ #define MEM_CFG_OFFSET 0x0 #define BURST_LEN_OFFSET 0x10 #define MEM_RESET_OFFSET 0x20 @@ -1340,6 +1341,7 @@ #define OFFSET_ADDR_OFFSET 0x380 #define INT_MON_STATUS_OFFSET 0x390 +/* OneNAND register */ #define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET) #define S5P_BURST_LEN S5P_ONENANDC_BASE(BURST_LEN_OFFSET) #define S5P_MEM_RESET S5P_ONENANDC_BASE(MEM_RESET_OFFSET) -- 2.7.4