From 8fa32a74cf1ddb44812505f30f2d970cd507adbb Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 27 Oct 2022 10:24:35 -0700 Subject: [PATCH] [RISCV] Fix an obvious CSE opportunity in LSR test case. NFC --- llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll index 25d32d7..4f11dcb 100644 --- a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll +++ b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll @@ -75,13 +75,12 @@ define void @test(i32 signext %i) nounwind { entry: %k_addr.012 = shl i32 %i, 1 %tmp14 = icmp sgt i32 %k_addr.012, 8192 - %tmp. = shl i32 %i, 1 br i1 %tmp14, label %return, label %bb bb: %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] %tmp.15 = mul i32 %indvar, %i - %tmp.16 = add i32 %tmp.15, %tmp. + %tmp.16 = add i32 %tmp.15, %k_addr.012 %gep.upgrd.1 = zext i32 %tmp.16 to i64 %tmp = getelementptr [8193 x i8], [8193 x i8]* @flags2, i32 0, i64 %gep.upgrd.1 store i8 0, i8* %tmp -- 2.7.4