From 8f8c10f3fada4c1464e44d7e8ae50dd827279d76 Mon Sep 17 00:00:00 2001 From: "Dharageswari.R" Date: Thu, 6 Oct 2011 16:18:28 +0100 Subject: [PATCH] intel_sst: Restore the csr value after S3 and S0i3 states The csr value is lost during S3 and the value was not restored back completely after system resume.So, audio playback fails after resume from S3 This patch stores the original value of csr before S3 and restores it back on resume. Change-Id: I80afeb939e4753f2baf05a0ad91b33ab4dc013a5 Signed-off-by: Dharageswari.R --- drivers/staging/intel_sst/intel_sst.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/staging/intel_sst/intel_sst.c b/drivers/staging/intel_sst/intel_sst.c index f37b643..96c9617 100644 --- a/drivers/staging/intel_sst/intel_sst.c +++ b/drivers/staging/intel_sst/intel_sst.c @@ -525,8 +525,14 @@ static int intel_sst_runtime_resume(struct device *dev) return 0; } csr = sst_shim_read(sst_drv_ctx->shim, SST_CSR); - csr |= sst_drv_ctx->csr_value; - sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr); + /* + * To restore the csr_value after S0ix and S3 states. + * The value 0x30000 is to enable LPE dram high and low addresses. + * Reference: + * Penwell Audio Voice Module HAS 1.61 Section - 13.12.1 - + * CSR - Configuration and Status Register. + */ + csr |= (sst_drv_ctx->csr_value | 0x30000); ipc_wbuf = (u32 *)&cbuf; cbuf[0] = 0; /* OSC_CLK_OUT0 */ -- 2.7.4