From 8f7b13218b01e287895c9906bca94f67f8bc25b9 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 27 Dec 2011 14:42:50 +0900 Subject: [PATCH] ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1 Amba core assumes the pclk to be named as apb_pclk. During device probe, it tries to get that clock and enable that. When PM_RUNTIME is enabled, dma clock is not explicitly enabled in pl330_probe, which causes device probe to fail. Adding a clkdev entry for apb_pclk for mdma1 fixes the problem. This patch fixes following runtime error. dma-pl330 dma-pl330.2: PERIPH_ID 0x0, PCELL_ID 0x0 ! dma-pl330: probe of dma-pl330.2 failed with error -22 Signed-off-by: Tushar Behera Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/clock-exynos4.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index db5d1cc..1bc0b75 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1338,6 +1338,7 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), + CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), -- 2.7.4