From 8f6eb35e0972e95127ab8ea984f915f7c3526544 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 24 Aug 2020 13:52:46 +1000 Subject: [PATCH] gallivm/nir: add some f16 support GLSL lowers packhalf2x16 itself, but for SPIRV we don't have that option. For packing when NIR lowers it uses f2f16 and for unpack it needs the casting and f2f32 Fixes: dEQP-VK.glsl.builtin.function.pack_unpack.packhalf2x16* dEQP-VK.glsl.builtin.function.pack_unpack.unpackhalf2x16* Reviewed-by: Roland Scheidegger Part-of: --- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index 9a60452..c008e22 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -46,6 +46,8 @@ static LLVMValueRef cast_type(struct lp_build_nir_context *bld_base, LLVMValueRe switch (alu_type) { case nir_type_float: switch (bit_size) { + case 16: + return LLVMBuildBitCast(builder, val, LLVMVectorType(LLVMHalfTypeInContext(bld_base->base.gallivm->context), bld_base->base.type.length), ""); case 32: return LLVMBuildBitCast(builder, val, bld_base->base.vec_type, ""); case 64: @@ -489,9 +491,17 @@ static LLVMValueRef do_alu_action(struct lp_build_nir_context *bld_base, case nir_op_f2b32: result = flt_to_bool32(bld_base, src_bit_size[0], src[0]); break; - case nir_op_f2f32: + case nir_op_f2f16: result = LLVMBuildFPTrunc(builder, src[0], - bld_base->base.vec_type, ""); + LLVMVectorType(LLVMHalfTypeInContext(gallivm->context), bld_base->base.type.length), ""); + break; + case nir_op_f2f32: + if (src_bit_size[0] < 32) + result = LLVMBuildFPExt(builder, src[0], + bld_base->base.vec_type, ""); + else + result = LLVMBuildFPTrunc(builder, src[0], + bld_base->base.vec_type, ""); break; case nir_op_f2f64: result = LLVMBuildFPExt(builder, src[0], -- 2.7.4