From 8f5bdb9d2837ac07d963c9273e32acd25542afd7 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 14 Oct 2016 20:52:43 +0000
Subject: [PATCH] [ARM] add tests for PR30660

llvm-svn: 284280
---
 llvm/test/CodeGen/ARM/negate-i1.ll | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 llvm/test/CodeGen/ARM/negate-i1.ll

diff --git a/llvm/test/CodeGen/ARM/negate-i1.ll b/llvm/test/CodeGen/ARM/negate-i1.ll
new file mode 100644
index 0000000..9633bcb
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/negate-i1.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+
+; PR30660 - https://llvm.org/bugs/show_bug.cgi?id=30660
+
+define i32 @select_i32_neg1_or_0(i1 %a) {
+; CHECK-LABEL: select_i32_neg1_or_0:
+; CHECK-NEXT:  @ BB#0:
+; CHECK-NEXT:    lsl r0, r0, #31
+; CHECK-NEXT:    asr r0, r0, #31
+; CHECK-NEXT:    mov pc, lr
+;
+  %b = sext i1 %a to i32
+  ret i32 %b
+}
+
+define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
+; CHECK-LABEL: select_i32_neg1_or_0_zeroext:
+; CHECK-NEXT:  @ BB#0:
+; CHECK-NEXT:    lsl r0, r0, #31
+; CHECK-NEXT:    asr r0, r0, #31
+; CHECK-NEXT:    mov pc, lr
+;
+  %b = sext i1 %a to i32
+  ret i32 %b
+}
+
-- 
2.7.4