From 8f323c712ea76cc4506b03895e9b991e4e4b2baf Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Tue, 7 Sep 2021 12:39:04 +0800
Subject: [PATCH] Optimize v4sf reduction.

gcc/ChangeLog:

	PR target/101059
	* config/i386/sse.md (reduc_plus_scal_<mode>): Split to ..
	(reduc_plus_scal_v4sf): .. this, New define_expand.
	(reduc_plus_scal_v2df): .. and this, New define_expand.

gcc/testsuite/ChangeLog:

	PR target/101059
	* gcc.target/i386/sse2-pr101059.c: New test.
	* gcc.target/i386/sse3-pr101059.c: New test.
---
 gcc/config/i386/sse.md                        | 39 +++++++++++++++++++--------
 gcc/testsuite/gcc.target/i386/sse2-pr101059.c | 32 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/i386/sse3-pr101059.c | 13 +++++++++
 3 files changed, 73 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/sse2-pr101059.c
 create mode 100644 gcc/testsuite/gcc.target/i386/sse3-pr101059.c

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ee81fdb..9c67750 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2995,19 +2995,36 @@
    (set_attr "prefix_rep" "1,*")
    (set_attr "mode" "V4SF")])
 
-(define_mode_iterator REDUC_SSE_PLUS_MODE
- [(V2DF "TARGET_SSE") (V4SF "TARGET_SSE")])
+(define_expand "reduc_plus_scal_v4sf"
+ [(plus:V4SF
+   (match_operand:SF 0 "register_operand")
+   (match_operand:V4SF 1 "register_operand"))]
+ "TARGET_SSE"
+{
+  rtx vtmp = gen_reg_rtx (V4SFmode);
+  rtx stmp = gen_reg_rtx (SFmode);
+  if (TARGET_SSE3)
+    emit_insn (gen_sse3_movshdup (vtmp, operands[1]));
+  else
+    emit_insn (gen_sse_shufps (vtmp, operands[1], operands[1], GEN_INT(177)));
 
-(define_expand "reduc_plus_scal_<mode>"
- [(plus:REDUC_SSE_PLUS_MODE
-   (match_operand:<ssescalarmode> 0 "register_operand")
-   (match_operand:REDUC_SSE_PLUS_MODE 1 "register_operand"))]
- ""
+  emit_insn (gen_addv4sf3 (operands[1], operands[1], vtmp));
+  emit_insn (gen_sse_movhlps (vtmp, vtmp, operands[1]));
+  emit_insn (gen_vec_extractv4sfsf (stmp, vtmp, const0_rtx));
+  emit_insn (gen_vec_extractv4sfsf (operands[0], operands[1], const0_rtx));
+  emit_insn (gen_addsf3 (operands[0], operands[0], stmp));
+  DONE;
+})
+
+(define_expand "reduc_plus_scal_v2df"
+ [(plus:V2DF
+   (match_operand:DF 0 "register_operand")
+   (match_operand:V2DF 1 "register_operand"))]
+ "TARGET_SSE"
 {
-  rtx tmp = gen_reg_rtx (<MODE>mode);
-  ix86_expand_reduc (gen_add<mode>3, tmp, operands[1]);
-  emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
-                                                        const0_rtx));
+  rtx tmp = gen_reg_rtx (V2DFmode);
+  ix86_expand_reduc (gen_addv2df3, tmp, operands[1]);
+  emit_insn (gen_vec_extractv2dfdf (operands[0], tmp, const0_rtx));
   DONE;
 })
 
diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr101059.c b/gcc/testsuite/gcc.target/i386/sse2-pr101059.c
new file mode 100644
index 0000000..d155bf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-pr101059.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+float
+__attribute__((noipa, optimize("tree-vectorize")))
+foo (float* p)
+{
+  float sum = 0.f;
+  for (int i = 0; i != 4; i++)
+    sum += p[i];
+  return sum;
+}
+
+static void
+TEST (void)
+{
+  float p[4] = {1.0f, 2.0f, 3.0f, 4.0f};
+  float res = foo (p);
+  if (res != 10.0f)
+    abort();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse3-pr101059.c b/gcc/testsuite/gcc.target/i386/sse3-pr101059.c
new file mode 100644
index 0000000..4795e89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse3-pr101059.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -msse3" } */
+/* { dg-require-effective-target sse3 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include "sse2-pr101059.c"
-- 
2.7.4