From 8f06e7dea415dc544e9073659fd6f387277d63b9 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 5 Oct 2012 18:41:14 +0000 Subject: [PATCH] [ms-inline asm] Add a few typedefs to simplify future changes. llvm-svn: 165324 --- llvm/include/llvm/MC/MCTargetAsmParser.h | 8 ++++++-- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- .../Target/MBlaze/AsmParser/MBlazeAsmParser.cpp | 2 +- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 2 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 +++--- llvm/utils/TableGen/AsmMatcherEmitter.cpp | 23 +++++++++++----------- 6 files changed, 24 insertions(+), 19 deletions(-) diff --git a/llvm/include/llvm/MC/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCTargetAsmParser.h index 16cf627..c5451ce 100644 --- a/llvm/include/llvm/MC/MCTargetAsmParser.h +++ b/llvm/include/llvm/MC/MCTargetAsmParser.h @@ -50,6 +50,10 @@ public: virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0; + typedef std::pair< unsigned, std::string > MapAndConstraint; + typedef SmallVector MatchInstMapAndConstraints; + typedef SmallVectorImpl MatchInstMapAndConstraintsImpl; + /// ParseInstruction - Parse one assembly instruction. /// /// The parser is positioned following the instruction name. The target @@ -92,7 +96,7 @@ public: MatchInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, MCStreamer &Out, unsigned &Kind, unsigned &Opcode, - SmallVectorImpl > &MapAndConstraints, + MatchInstMapAndConstraintsImpl &MapAndConstraints, unsigned &OrigErrorInfo, bool matchingInlineAsm = false) { OrigErrorInfo = ~0x0; return true; @@ -117,7 +121,7 @@ public: virtual void convertToMapAndConstraints(unsigned Kind, const SmallVectorImpl &Operands, - SmallVectorImpl > &MapAndConstraints) = 0; + MatchInstMapAndConstraintsImpl &MapAndConstraints) = 0; }; } // End llvm namespace diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 9e92649..00f0f74 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7480,7 +7480,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned Kind; unsigned ErrorInfo; unsigned MatchResult; - SmallVector, 4> MapAndConstraints; + MatchInstMapAndConstraints MapAndConstraints; MatchResult = MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints, ErrorInfo, /*matchingInlineAsm*/ false); diff --git a/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp b/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp index 09eb4c8..d1e18b2 100644 --- a/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp +++ b/llvm/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp @@ -318,7 +318,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, MCInst Inst; unsigned Kind; unsigned ErrorInfo; - SmallVector, 4> MapAndConstraints; + MatchInstMapAndConstraints MapAndConstraints; switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints, ErrorInfo, /*matchingInlineAsm*/ false)) { default: break; diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index f2800d3..6605fe4 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -371,7 +371,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, MCInst Inst; unsigned Kind; unsigned ErrorInfo; - SmallVector, 4> MapAndConstraints; + MatchInstMapAndConstraints MapAndConstraints; unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints, ErrorInfo, /*matchingInlineAsm*/ false); diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 24f57e0..df34359 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -69,7 +69,7 @@ private: bool MatchInstruction(SMLoc IDLoc, SmallVectorImpl &Operands, MCStreamer &Out, unsigned &Kind, unsigned &Opcode, - SmallVectorImpl > &MapAndConstraints, + MatchInstMapAndConstraintsImpl &MapAndConstraints, unsigned &OrigErrorInfo, bool matchingInlineAsm = false); /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi) @@ -1526,7 +1526,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned Kind; unsigned Opcode; unsigned ErrorInfo; - SmallVector, 4> MapAndConstraints; + MatchInstMapAndConstraints MapAndConstraints; bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode, MapAndConstraints, ErrorInfo); return Error; @@ -1631,7 +1631,7 @@ MatchInstruction(SMLoc IDLoc, unsigned Match1, Match2, Match3, Match4; unsigned tKind; - SmallVector, 4> tMapAndConstraints[4]; + MatchInstMapAndConstraints tMapAndConstraints[4]; Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0], ErrorInfoIgnore, isParsingIntelSyntax()); if (Match1 == Match_Success) Kind = tKind; diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index cde9e1c..435baee 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -1716,9 +1716,9 @@ static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName, OpOS << "void " << Target.getName() << ClassName << "::\n" << "convertToMapAndConstraints(unsigned Kind,\n"; OpOS.indent(27); - OpOS << "const SmallVectorImpl &Operands,\n" - << " SmallVectorImpl >" - << " &MapAndConstraints) {\n" + OpOS << "const SmallVectorImpl &Operands,\n"; + OpOS.indent(27); + OpOS << "MatchInstMapAndConstraintsImpl &MapAndConstraints) {\n" << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" << " unsigned NumMCOperands = 0;\n" << " const uint8_t *Converter = ConversionTable[Kind];\n" @@ -2606,15 +2606,16 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << " const SmallVectorImpl " << "&Operands);\n"; OS << " void convertToMapAndConstraints(unsigned Kind,\n "; - OS << " const SmallVectorImpl &Operands,\n" - << " SmallVectorImpl >" - << " &MapAndConstraints);\n"; + OS << " const SmallVectorImpl &Operands,\n"; + OS.indent(29); + OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints);\n"; OS << " bool mnemonicIsValid(StringRef Mnemonic);\n"; - OS << " unsigned MatchInstructionImpl(\n" - << " const SmallVectorImpl &Operands,\n" - << " unsigned &Kind, MCInst &Inst,\n" - << " SmallVectorImpl > " - << "&MapAndConstraints,\n" + OS << " unsigned MatchInstructionImpl(\n"; + OS.indent(27); + OS << "const SmallVectorImpl &Operands,\n" + << " unsigned &Kind, MCInst &Inst,\n"; + OS.indent(30); + OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints,\n" << " unsigned &ErrorInfo," << " bool matchingInlineAsm,\n" << " unsigned VariantID = 0);\n"; -- 2.7.4