From 8e92b402030735edab6c35e69dceee4acebb973b Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Thu, 15 Sep 2016 10:49:40 +0200 Subject: [PATCH] i965/vec4/tes: consider register offsets during attribute setup Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_vec4_tes.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp index bb81ad3..ae6d99b 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tes.cpp @@ -84,8 +84,8 @@ vec4_tes_visitor::setup_payload() bool is_64bit = type_sz(inst->src[i].type) == 8; - struct brw_reg grf = - brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2)); + unsigned slot = inst->src[i].nr + inst->src[i].offset / 16; + struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2)); grf = stride(grf, 0, is_64bit ? 2 : 4, 1); grf.swizzle = inst->src[i].swizzle; grf.type = inst->src[i].type; -- 2.7.4