From 8e84c9ae99846c91c4e9828f1945c200d26d2fb9 Mon Sep 17 00:00:00 2001 From: Stefan Pintilie Date: Wed, 27 Nov 2019 15:38:05 -0600 Subject: [PATCH] [PowerPC] Separate Features that are known to be Power9 specific from Future CPU The Power 9 CPU has some features that are unlikely to be passed on to future versions of the CPU. This patch separates this out so that future CPU does not inherit them. Differential Revision: https://reviews.llvm.org/D70466 --- llvm/lib/Target/PowerPC/PPC.td | 17 +++++++++++++---- .../Analysis/CostModel/PowerPC/future-cost-model.ll | 16 ++++++++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 6fa46f0..a83bfc5 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -237,13 +237,22 @@ def ProcessorFeatures { list Power8FeatureList = !listconcat(Power7FeatureList, Power8SpecificFeatures); list Power9SpecificFeatures = - [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0, - FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched]; + [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0]; + + // Some features are unique to Power9 and there is no reason to assume + // they will be part of any future CPUs. One example is the narrower + // dispatch for vector operations than scalar ones. For the time being, + // this list also includes scheduling-related features since we do not have + // enough info to create custom scheduling strategies for future CPUs. + list Power9OnlyFeatures = + [FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched]; list Power9FeatureList = !listconcat(Power8FeatureList, Power9SpecificFeatures); + list Power9ImplList = + !listconcat(Power9FeatureList, Power9OnlyFeatures); // For future CPU we assume that all of the existing features from Power 9 - // still exist. + // still exist with the exception of those we know are Power 9 specific. list FutureSpecificFeatures = []; list FutureFeatureList = @@ -449,7 +458,7 @@ def : ProcessorModel<"pwr6x", G5Model, FeatureMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; -def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>; +def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9ImplList>; // No scheduler model for future CPU. def : ProcessorModel<"future", NoSchedModel, ProcessorFeatures.FutureFeatureList>; diff --git a/llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll b/llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll new file mode 100644 index 0000000..3e4fb82 --- /dev/null +++ b/llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future | FileCheck %s --check-prefix=FUTURE +; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr9 | FileCheck %s --check-prefix=PWR9 + +define void @test(i16 %p1, i16 %p2, <4 x i16> %p3, <4 x i16> %p4) { + %i1 = add i16 %p1, %p2 + %v1 = add <4 x i16> %p3, %p4 + ret void + ; FUTURE: cost of 1 {{.*}} add + ; FUTURE: cost of 1 {{.*}} add + + ; PWR9: cost of 1 {{.*}} add + ; PWR9: cost of 2 {{.*}} add +} + -- 2.7.4