From 8e793f18ee5ca5815730026a71ef3b93d5f401a4 Mon Sep 17 00:00:00 2001 From: hubicka Date: Sat, 16 Nov 2002 01:09:19 +0000 Subject: [PATCH] * athlon.md, k6.md, pentium.md, ppro.md: Handle shift1, rotate1 * i386.md (attribute type): Add type shift1 and rotate1. (*_slp): Rewrite to have just two operands to avoid reload problems. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@59147 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 +++ gcc/config/i386/athlon.md | 2 +- gcc/config/i386/i386.md | 119 +++++++++++++++++++++++---------------------- gcc/config/i386/k6.md | 4 +- gcc/config/i386/pentium.md | 6 +++ gcc/config/i386/ppro.md | 2 +- 6 files changed, 77 insertions(+), 62 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 91f0aff..7490076 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Sat Nov 16 02:06:02 CET 2002 Jan Hubicka + + * athlon.md, k6.md, pentium.md, ppro.md: Handle shift1, rotate1 + * i386.md (attribute type): Add type shift1 and rotate1. + (*_slp): Rewrite to have just two operands to avoid reload problems. + 2002-11-15 Kazu Hirata * config/h8300/h8300.md (4 anonymous patterns): New. diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index d6a52f2..548f2ad 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -63,7 +63,7 @@ (define_function_unit "athlon_ieu" 3 0 (and (eq_attr "cpu" "athlon") - (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,rotate,ibr,call,callv,icmov,cld,pop,setcc,push,pop")) + (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ishift1,rotate,rotate1,ibr,call,callv,icmov,cld,pop,setcc,push,pop")) 1 1) (define_function_unit "athlon_ieu" 3 0 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4596cee..7f9de52 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -140,7 +140,7 @@ (define_attr "type" "other,multi, alu,alu1,negnot,imov,imovx,lea, - incdec,ishift,rotate,imul,idiv, + incdec,ishift,ishift1,rotate,rotate1,imul,idiv, icmp,test,ibr,setcc,icmov, push,pop,call,callv, str,cld, @@ -174,8 +174,8 @@ (const_int 0) (eq_attr "unit" "i387,sse,mmx") (const_int 0) - (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,imul, - icmp,push,pop") + (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1, + imul,icmp,push,pop") (symbol_ref "ix86_attr_length_immediate_default(insn,1)") (eq_attr "type" "imov,test") (symbol_ref "ix86_attr_length_immediate_default(insn,0)") @@ -347,7 +347,7 @@ (define_attr "imm_disp" "false,true,unknown" (cond [(eq_attr "type" "other,multi") (const_string "unknown") - (and (eq_attr "type" "icmp,test,imov") + (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1") (and (match_operand 0 "memory_displacement_operand" "") (match_operand 1 "immediate_operand" ""))) (const_string "true") @@ -6040,11 +6040,11 @@ (define_insn "*addqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) - (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0") - (match_operand:QI 2 "general_operand" "qn,qnm"))) + (plus:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "qn,qnm"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (PLUS, QImode, operands)" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (get_attr_type (insn)) { @@ -6061,9 +6061,9 @@ && INTVAL (operands[2]) < 0) { operands[2] = GEN_INT (-INTVAL (operands[2])); - return "sub{b}\t{%2, %0|%0, %2}"; + return "sub{b}\t{%1, %0|%0, %1}"; } - return "add{b}\t{%2, %0|%0, %2}"; + return "add{b}\t{%1, %0|%0, %1}"; } } [(set (attr "type") @@ -6605,12 +6605,12 @@ (define_insn "*subqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) - (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "general_operand" "qn,qmn"))) + (minus:QI (match_dup 0) + (match_operand:QI 1 "general_operand" "qn,qmn"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (MINUS, QImode, operands)" - "sub{b}\t{%2, %0|%0, %2}" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + "sub{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu") (set_attr "mode" "QI")]) @@ -8067,7 +8067,8 @@ (and:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qi,qmi"))) (clobber (reg:CC 17))] - "! TARGET_PARTIAL_REG_STALL || optimize_size" + "(! TARGET_PARTIAL_REG_STALL || optimize_size) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "and{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8104,7 +8105,8 @@ (set (strict_low_part (match_dup 0)) (and:QI (match_dup 0) (match_dup 1)))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_match_ccmode (insn, CCNOmode)" + && ix86_match_ccmode (insn, CCNOmode) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "and{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8474,7 +8476,8 @@ (ior:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qmi,qi"))) (clobber (reg:CC 17))] - "! TARGET_PARTIAL_REG_STALL || optimize_size" + "(! TARGET_PARTIAL_REG_STALL || optimize_size) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "or{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8500,7 +8503,8 @@ (set (strict_low_part (match_dup 0)) (ior:QI (match_dup 0) (match_dup 1)))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_match_ccmode (insn, CCNOmode)" + && ix86_match_ccmode (insn, CCNOmode) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "or{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8849,7 +8853,8 @@ (xor:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qi,qmi"))) (clobber (reg:CC 17))] - "! TARGET_PARTIAL_REG_STALL || optimize_size" + "(! TARGET_PARTIAL_REG_STALL || optimize_size) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "xor{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8949,7 +8954,8 @@ (set (strict_low_part (match_dup 0)) (xor:QI (match_dup 0) (match_dup 1)))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_match_ccmode (insn, CCNOmode)" + && ix86_match_ccmode (insn, CCNOmode) + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "xor{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -11511,14 +11517,14 @@ (define_insn "*ashrqi3_1_one_bit_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_int_1_operand" ""))) + (ashiftrt:QI (match_dup 0) + (match_operand:QI 1 "const_int_1_operand" ""))) (clobber (reg:CC 17))] "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) && (! TARGET_PARTIAL_REG_STALL || optimize_size) && (TARGET_SHIFT1 || optimize_size)" "sar{b}\t%0" - [(set_attr "type" "ishift") + [(set_attr "type" "ishift1") (set (attr "length") (if_then_else (match_operand 0 "register_operand" "") (const_string "2") @@ -11538,15 +11544,15 @@ (define_insn "*ashrqi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) - (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) + (ashiftrt:QI (match_dup 0) + (match_operand:QI 1 "nonmemory_operand" "I,c"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - sar{b}\t{%2, %0|%0, %2} - sar{b}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "ishift") + sar{b}\t{%1, %0|%0, %1} + sar{b}\t{%b1, %0|%0, %b1}" + [(set_attr "type" "ishift1") (set_attr "mode" "QI")]) ;; This pattern can't accept a variable shift count, since shifts by @@ -11930,14 +11936,13 @@ (define_insn "*lshrqi3_1_one_bit_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) - (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_int_1_operand" ""))) + (lshiftrt:QI (match_dup 0) + (match_operand:QI 1 "const_int_1_operand" ""))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (LSHIFTRT, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{b}\t%0" - [(set_attr "type" "ishift") + [(set_attr "type" "ishift1") (set (attr "length") (if_then_else (match_operand 0 "register_operand" "") (const_string "2") @@ -11957,15 +11962,15 @@ (define_insn "*lshrqi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) - (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) + (lshiftrt:QI (match_dup 0) + (match_operand:QI 1 "nonmemory_operand" "I,c"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - shr{b}\t{%2, %0|%0, %2} - shr{b}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "ishift") + shr{b}\t{%1, %0|%0, %1} + shr{b}\t{%b1, %0|%0, %b1}" + [(set_attr "type" "ishift1") (set_attr "mode" "QI")]) ;; This pattern can't accept a variable shift count, since shifts by @@ -12145,14 +12150,13 @@ (define_insn "*rotlqi3_1_one_bit_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) - (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_int_1_operand" ""))) + (rotate:QI (match_dup 0) + (match_operand:QI 1 "const_int_1_operand" ""))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (ROTATE, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{b}\t%0" - [(set_attr "type" "rotate") + [(set_attr "type" "rotate1") (set (attr "length") (if_then_else (match_operand 0 "register_operand" "") (const_string "2") @@ -12174,15 +12178,15 @@ (define_insn "*rotlqi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) - (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) + (rotate:QI (match_dup 0) + (match_operand:QI 1 "nonmemory_operand" "I,c"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (ROTATE, QImode, operands)" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - rol{b}\t{%2, %0|%0, %2} - rol{b}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "rotate") + rol{b}\t{%1, %0|%0, %1} + rol{b}\t{%b1, %0|%0, %b1}" + [(set_attr "type" "rotate1") (set_attr "mode" "QI")]) (define_insn "*rotlqi3_1" @@ -12351,14 +12355,13 @@ (define_insn "*rotrqi3_1_one_bit_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) - (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") - (match_operand:QI 2 "const_int_1_operand" ""))) + (rotatert:QI (match_dup 0) + (match_operand:QI 1 "const_int_1_operand" ""))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (ROTATERT, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{b}\t%0" - [(set_attr "type" "rotate") + [(set_attr "type" "rotate1") (set (attr "length") (if_then_else (match_operand 0 "register_operand" "") (const_string "2") @@ -12378,15 +12381,15 @@ (define_insn "*rotrqi3_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) - (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") - (match_operand:QI 2 "nonmemory_operand" "I,c"))) + (rotatert:QI (match_dup 0) + (match_operand:QI 1 "nonmemory_operand" "I,c"))) (clobber (reg:CC 17))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) - && ix86_binary_operator_ok (ROTATERT, QImode, operands)" + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - ror{b}\t{%2, %0|%0, %2} - ror{b}\t{%b2, %0|%0, %b2}" - [(set_attr "type" "rotate") + ror{b}\t{%1, %0|%0, %1} + ror{b}\t{%b1, %0|%0, %b1}" + [(set_attr "type" "rotate1") (set_attr "mode" "QI")]) ;; Bit set / bit test instructions diff --git a/gcc/config/i386/k6.md b/gcc/config/i386/k6.md index a68983a..af128bf 100644 --- a/gcc/config/i386/k6.md +++ b/gcc/config/i386/k6.md @@ -42,7 +42,7 @@ ;; Shift instructions and certain arithmetic are issued only to X pipe. (define_function_unit "k6_alux" 1 0 (and (eq_attr "cpu" "k6") - (eq_attr "type" "ishift,rotate,alu1,negnot,cld")) + (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld")) 1 1) ;; The QI mode arithmetic is issued to X pipe only. @@ -54,7 +54,7 @@ (define_function_unit "k6_alu" 2 0 (and (eq_attr "cpu" "k6") - (eq_attr "type" "ishift,rotate,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea")) + (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea")) 1 1) (define_function_unit "k6_alu" 2 0 diff --git a/gcc/config/i386/pentium.md b/gcc/config/i386/pentium.md index 4078955..b4c5ece 100644 --- a/gcc/config/i386/pentium.md +++ b/gcc/config/i386/pentium.md @@ -53,6 +53,12 @@ (and (eq_attr "type" "rotate") (match_operand 2 "const_int_1_operand" "")) (const_string "pu") + (and (eq_attr "type" "ishift1") + (match_operand 1 "const_int_operand" "")) + (const_string "pu") + (and (eq_attr "type" "rotate1") + (match_operand 1 "const_int_1_operand" "")) + (const_string "pu") (and (eq_attr "type" "call") (match_operand 0 "constant_call_address_operand" "")) (const_string "pv") diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md index f7afa4f..8690685 100644 --- a/gcc/config/i386/ppro.md +++ b/gcc/config/i386/ppro.md @@ -60,7 +60,7 @@ (define_function_unit "ppro_p0" 1 0 (and (eq_attr "cpu" "pentiumpro") - (eq_attr "type" "ishift,rotate,lea,ibr,cld")) + (eq_attr "type" "ishift,rotate,ishift1,rotate1,lea,ibr,cld")) 1 1) (define_function_unit "ppro_p0" 1 0 -- 2.7.4