From 8e3d9a7c4798f7fdd63f14c0331fcb978b2eafbb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 8 Apr 2021 22:34:44 +0530 Subject: [PATCH] ARM: dts: qcom: sdx55: Add support for APCS block The APCS block on SDX55 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210408170457.91409-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-sdx55.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 41c90f5..8112a52 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -360,6 +360,15 @@ #clock-cells = <0>; }; + apcs: mailbox@17810000 { + compatible = "qcom,sdx55-apcs-gcc", "syscon"; + reg = <0x17810000 0x2000>; + #mbox-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; + clock-names = "ref", "pll", "aux"; + #clock-cells = <0>; + }; + watchdog@17817000 { compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; reg = <0x17817000 0x1000>; -- 2.7.4