From 8e2e9d6f4c295deb72a1b8f7b7f4c4adbc317460 Mon Sep 17 00:00:00 2001 From: Pirama Arumuga Nainar Date: Fri, 18 Mar 2016 16:58:36 +0000 Subject: [PATCH] Add -fnative-half-arguments-and-returns Summary: r246764 handled __fp16 arguments and returns for AAPCS, but skipped this handling for OpenCL. Simlar to OpenCL, RenderScript also handles __fp16 type natively. This patch adds the -fnative-half-arguments-and-returns command line flag to allow such languages to skip this coercion of __fp16. Reviewers: srhines, olista01 Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18138 llvm-svn: 263795 --- clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Driver/CC1Options.td | 2 ++ clang/lib/CodeGen/TargetInfo.cpp | 4 ++-- clang/lib/Frontend/CompilerInvocation.cpp | 7 ++++++- clang/test/CodeGen/arm-fp16-arguments.c | 6 ++++++ 5 files changed, 17 insertions(+), 3 deletions(-) diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 623e896..55ceb0f 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -163,6 +163,7 @@ LANGOPT(ShortEnums , 1, 0, "short enum types") LANGOPT(OpenCL , 1, 0, "OpenCL") LANGOPT(OpenCLVersion , 32, 0, "OpenCL version") LANGOPT(NativeHalfType , 1, 0, "Native half type support") +LANGOPT(NativeHalfArgsAndReturns, 1, 0, "Native half args and returns") LANGOPT(HalfArgsAndReturns, 1, 0, "half args and returns") LANGOPT(CUDA , 1, 0, "CUDA") LANGOPT(OpenMP , 1, 0, "OpenMP support") diff --git a/clang/include/clang/Driver/CC1Options.td b/clang/include/clang/Driver/CC1Options.td index 5dc62ea..56efff07a 100644 --- a/clang/include/clang/Driver/CC1Options.td +++ b/clang/include/clang/Driver/CC1Options.td @@ -603,6 +603,8 @@ def fno_rtti_data : Flag<["-"], "fno-rtti-data">, HelpText<"Control emission of RTTI data">; def fnative_half_type: Flag<["-"], "fnative-half-type">, HelpText<"Use the native half type for __fp16 instead of promoting to float">; +def fnative_half_arguments_and_returns : Flag<["-"], "fnative-half-arguments-and-returns">, + HelpText<"Use the native __fp16 type for arguments and returns (and skip ABI-specific lowering)">; def fallow_half_arguments_and_returns : Flag<["-"], "fallow-half-arguments-and-returns">, HelpText<"Allow function arguments and returns of type half">; diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 1748cd2..de568b5 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -5106,7 +5106,7 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, // __fp16 gets passed as if it were an int or float, but with the top 16 bits // unspecified. This is not done for OpenCL as it handles the half type // natively, and does not need to interwork with AAPCS code. - if (Ty->isHalfType() && !getContext().getLangOpts().OpenCL) { + if (Ty->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) { llvm::Type *ResType = IsEffectivelyAAPCS_VFP ? llvm::Type::getFloatTy(getVMContext()) : llvm::Type::getInt32Ty(getVMContext()); @@ -5298,7 +5298,7 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy, // __fp16 gets returned as if it were an int or float, but with the top 16 // bits unspecified. This is not done for OpenCL as it handles the half type // natively, and does not need to interwork with AAPCS code. - if (RetTy->isHalfType() && !getContext().getLangOpts().OpenCL) { + if (RetTy->isHalfType() && !getContext().getLangOpts().NativeHalfArgsAndReturns) { llvm::Type *ResType = IsEffectivelyAAPCS_VFP ? llvm::Type::getFloatTy(getVMContext()) : llvm::Type::getInt32Ty(getVMContext()); diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index fe0ee97..6a88e3e 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1434,6 +1434,7 @@ void CompilerInvocation::setLangDefaults(LangOptions &Opts, InputKind IK, Opts.LaxVectorConversions = 0; Opts.DefaultFPContract = 1; Opts.NativeHalfType = 1; + Opts.NativeHalfArgsAndReturns = 1; } Opts.CUDA = IK == IK_CUDA || IK == IK_PreprocessedCuda || @@ -1795,7 +1796,11 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, Opts.ModuleFeatures = Args.getAllArgValues(OPT_fmodule_feature); std::sort(Opts.ModuleFeatures.begin(), Opts.ModuleFeatures.end()); Opts.NativeHalfType |= Args.hasArg(OPT_fnative_half_type); - Opts.HalfArgsAndReturns = Args.hasArg(OPT_fallow_half_arguments_and_returns); + Opts.NativeHalfArgsAndReturns |= Args.hasArg(OPT_fnative_half_arguments_and_returns); + // Enable HalfArgsAndReturns if present in Args or if NativeHalfArgsAndReturns + // is enabled. + Opts.HalfArgsAndReturns = Args.hasArg(OPT_fallow_half_arguments_and_returns) + | Opts.NativeHalfArgsAndReturns; Opts.GNUAsm = !Args.hasArg(OPT_fno_gnu_inline_asm); // __declspec is enabled by default for the PS4 by the driver, and also diff --git a/clang/test/CodeGen/arm-fp16-arguments.c b/clang/test/CodeGen/arm-fp16-arguments.c index 15a9ceb..65f076a 100644 --- a/clang/test/CodeGen/arm-fp16-arguments.c +++ b/clang/test/CodeGen/arm-fp16-arguments.c @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT // RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi hard -fallow-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD +// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs -mfloat-abi soft -fnative-half-arguments-and-returns -emit-llvm -o - -O1 %s | FileCheck %s --check-prefix=NATIVE __fp16 g; @@ -10,12 +11,17 @@ void t1(__fp16 a) { g = a; } // HARD: [[BITCAST:%.*]] = bitcast float [[PARAM]] to i32 // HARD: [[TRUNC:%.*]] = trunc i32 [[BITCAST]] to i16 // CHECK: store i16 [[TRUNC]], i16* bitcast (half* @g to i16*) +// NATIVE: define void @t1(half [[PARAM:%.*]]) +// NATIVE: store half [[PARAM]], half* @g __fp16 t2() { return g; } // SOFT: define i32 @t2() // HARD: define arm_aapcs_vfpcc float @t2() +// NATIVE: define half @t2() // CHECK: [[LOAD:%.*]] = load i16, i16* bitcast (half* @g to i16*) // CHECK: [[ZEXT:%.*]] = zext i16 [[LOAD]] to i32 // SOFT: ret i32 [[ZEXT]] // HARD: [[BITCAST:%.*]] = bitcast i32 [[ZEXT]] to float // HARD: ret float [[BITCAST]] +// NATIVE: [[LOAD:%.*]] = load half, half* @g +// NATIVE: ret half [[LOAD]] -- 2.7.4