From 8da03df56724152e4f524160b68e63c615d4632a Mon Sep 17 00:00:00 2001 From: Matthew Malcomson Date: Tue, 24 Jul 2018 15:37:52 +0000 Subject: [PATCH] [GCC][AARCH64] Canonicalize aarch64 widening simd plus insns Committed on behalf of matthew.malcomson@arm.com 2018-07-24 Matthew Malcomson * config/aarch64/aarch64-simd.md (aarch64_w): Split into... (aarch64_subw): ... This... (aarch64_addw): ... And this. (aarch64_w_internal): Split into... (aarch64_subw_internal): ... This... (aarch64_addw_internal): ... And this. (aarch64_w2_internal): Split into... (aarch64_subw2_internal): ... This... (aarch64_addw2_internal): ... And this. * gcc.target/aarch64/vect-su-add-sub.c: New. From-SVN: r262949 --- gcc/ChangeLog | 13 ++++ gcc/config/aarch64/aarch64-simd.md | 80 ++++++++++++++++------ gcc/testsuite/ChangeLog | 4 ++ .../gcc.target/aarch64/simd/vect_su_add_sub.c | 49 +++++++++++++ 4 files changed, 124 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7b921b..f1fdb1f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2018-07-24 Matthew Malcomson + + * config/aarch64/aarch64-simd.md + (aarch64_w): Split into... + (aarch64_subw): ... This... + (aarch64_addw): ... And this. + (aarch64_w_internal): Split into... + (aarch64_subw_internal): ... This... + (aarch64_addw_internal): ... And this. + (aarch64_w2_internal): Split into... + (aarch64_subw2_internal): ... This... + (aarch64_addw2_internal): ... And this. + 2018-07-24 Jakub Jelinek PR middle-end/86627 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f1784d7..9ee9bbe 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3303,38 +3303,74 @@ DONE; }) -(define_insn "aarch64_w" +(define_insn "aarch64_subw" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (match_operand:VD_BHSI 2 "register_operand" "w"))))] + (minus: (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (match_operand:VD_BHSI 2 "register_operand" "w"))))] "TARGET_SIMD" - "w\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "subw\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_w_internal" +(define_insn "aarch64_subw_internal" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (vec_select: - (match_operand:VQW 2 "register_operand" "w") - (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] + (minus: (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))] "TARGET_SIMD" - "w\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "subw\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] ) -(define_insn "aarch64_w2_internal" +(define_insn "aarch64_subw2_internal" [(set (match_operand: 0 "register_operand" "=w") - (ADDSUB: (match_operand: 1 "register_operand" "w") - (ANY_EXTEND: - (vec_select: - (match_operand:VQW 2 "register_operand" "w") - (match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))] + (minus: (match_operand: 1 "register_operand" "w") + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))] "TARGET_SIMD" - "w2\\t%0., %1., %2." - [(set_attr "type" "neon__widen")] + "subw2\\t%0., %1., %2." + [(set_attr "type" "neon_sub_widen")] +) + +(define_insn "aarch64_addw" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: (match_operand:VD_BHSI 2 "register_operand" "w")) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "addw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_addw_internal" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "addw\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] +) + +(define_insn "aarch64_addw2_internal" + [(set (match_operand: 0 "register_operand" "=w") + (plus: + (ANY_EXTEND: + (vec_select: + (match_operand:VQW 2 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) + (match_operand: 1 "register_operand" "w")))] + "TARGET_SIMD" + "addw2\\t%0., %1., %2." + [(set_attr "type" "neon_add_widen")] ) (define_expand "aarch64_saddw2" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ca4d0bc..10488ca 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-07-24 Matthew Malcomson + + * gcc.target/aarch64/vect-su-add-sub.c: New. + 2018-07-24 Jakub Jelinek PR middle-end/86627 diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c new file mode 100644 index 0000000..338da54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c @@ -0,0 +1,49 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* Ensure we use the signed/unsigned extend vectorized add and sub + instructions. */ +#define N 1024 + +int a[N]; +long c[N]; +long d[N]; +unsigned int ua[N]; +unsigned long uc[N]; +unsigned long ud[N]; + +void +add () +{ + for (int i = 0; i < N; i++) + d[i] = a[i] + c[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]saddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]saddw\[ \t\]+" 1 } } */ + +void +subtract () +{ + for (int i = 0; i < N; i++) + d[i] = c[i] - a[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]ssubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]ssubw\[ \t\]+" 1 } } */ + +void +uadd () +{ + for (int i = 0; i < N; i++) + ud[i] = ua[i] + uc[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]uaddw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]uaddw\[ \t\]+" 1 } } */ + +void +usubtract () +{ + for (int i = 0; i < N; i++) + ud[i] = uc[i] - ua[i]; +} +/* { dg-final { scan-assembler-times "\[ \t\]usubw2\[ \t\]+" 1 } } */ +/* { dg-final { scan-assembler-times "\[ \t\]usubw\[ \t\]+" 1 } } */ -- 2.7.4