From 8d1376c60e78f1fcc8faea2bfdac6b8641509e40 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 8 Dec 2014 20:33:01 +0000 Subject: [PATCH] [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions. llvm-svn: 223692 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 104 +++++++++++++++++++++++- llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt | 50 ++++++++++++ 2 files changed, 152 insertions(+), 2 deletions(-) create mode 100644 llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 70f07e6..0c7f9ce 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -961,8 +961,108 @@ def TSTBIT_ri : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), //===----------------------------------------------------------------------===// // ALU64/ALU + -//===----------------------------------------------------------------------===// -// Add. +//===----------------------------------------------------------------------===//// Add. +//===----------------------------------------------------------------------===// +// Template Class +// Add/Subtract halfword +// Rd=add(Rt.L,Rs.[HL])[:sat] +// Rd=sub(Rt.L,Rs.[HL])[:sat] +// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] +// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] +//===----------------------------------------------------------------------===// + +let hasNewValue = 1, opNewValue = 0 in +class T_XTYPE_ADD_SUB LHbits, bit isSat, bit hasShift, bit isSub> + : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), + "$Rd = "#!if(isSub,"sub","add")#"($Rt." + #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs." + #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)")) + #!if(isSat,":sat","") + #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> { + bits<5> Rd; + bits<5> Rt; + bits<5> Rs; + let IClass = 0b1101; + + let Inst{27-23} = 0b01010; + let Inst{22} = hasShift; + let Inst{21} = isSub; + let Inst{7} = isSat; + let Inst{6-5} = LHbits; + let Inst{4-0} = Rd; + let Inst{12-8} = Rt; + let Inst{20-16} = Rs; + } + +//Rd=sub(Rt.L,Rs.[LH]) +let isCodeGenOnly = 0 in { +def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>; +def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>; +} + +let isCodeGenOnly = 0 in { +//Rd=add(Rt.L,Rs.[LH]) +def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>; +def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>; +} + +let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in { + //Rd=sub(Rt.L,Rs.[LH]):sat + def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>; + def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>; + + //Rd=add(Rt.L,Rs.[LH]):sat + def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>; + def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>; +} + +//Rd=sub(Rt.[LH],Rs.[LH]):<<16 +let isCodeGenOnly = 0 in { +def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>; +def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>; +def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>; +def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>; +} + +//Rd=add(Rt.[LH],Rs.[LH]):<<16 +let isCodeGenOnly = 0 in { +def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>; +def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>; +def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>; +def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>; +} + +let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in { + //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 + def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>; + def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>; + def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>; + def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>; + + //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 + def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>; + def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>; + def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>; + def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>; +} + +// Add halfword. +def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16), + (A2_addh_l16_ll I32:$src1, I32:$src2)>; + +def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)), + (A2_addh_l16_hl I32:$src1, I32:$src2)>; + +def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)), + (A2_addh_h16_ll I32:$src1, I32:$src2)>; + +// Subtract halfword. +def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16), + (A2_subh_l16_ll I32:$src1, I32:$src2)>; + +def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)), + (A2_subh_h16_ll I32:$src1, I32:$src2)>; + def ADD64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2), "$dst = add($src1, $src2)", diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt new file mode 100644 index 0000000..b5f8cbc --- /dev/null +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s + +0x11 0xd5 0x1f 0xd5 +# CHECK: r17 = add(r21.l, r31.l) +0x51 0xd5 0x1f 0xd5 +# CHECK: r17 = add(r21.l, r31.h) +0x91 0xd5 0x1f 0xd5 +# CHECK: r17 = add(r21.l, r31.l):sat +0xd1 0xd5 0x1f 0xd5 +# CHECK: r17 = add(r21.l, r31.h):sat +0x11 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.l, r31.l):<<16 +0x31 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.l, r31.h):<<16 +0x51 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.h, r31.l):<<16 +0x71 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.h, r31.h):<<16 +0x91 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.l, r31.l):sat:<<16 +0xb1 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.l, r31.h):sat:<<16 +0xd1 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.h, r31.l):sat:<<16 +0xf1 0xd5 0x5f 0xd5 +# CHECK: r17 = add(r21.h, r31.h):sat:<<16 +0x11 0xd5 0x3f 0xd5 +# CHECK: r17 = sub(r21.l, r31.l) +0x51 0xd5 0x3f 0xd5 +# CHECK: r17 = sub(r21.l, r31.h) +0x91 0xd5 0x3f 0xd5 +# CHECK: r17 = sub(r21.l, r31.l):sat +0xd1 0xd5 0x3f 0xd5 +# CHECK: r17 = sub(r21.l, r31.h):sat +0x11 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.l, r31.l):<<16 +0x31 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.l, r31.h):<<16 +0x51 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.h, r31.l):<<16 +0x71 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.h, r31.h):<<16 +0x91 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.l, r31.l):sat:<<16 +0xb1 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.l, r31.h):sat:<<16 +0xd1 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.h, r31.l):sat:<<16 +0xf1 0xd5 0x7f 0xd5 +# CHECK: r17 = sub(r21.h, r31.h):sat:<<16 -- 2.7.4