From 8ca5be93cc764475a0f7caf6ed68e62ac819f61e Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Tue, 22 Feb 2022 18:06:47 +0000 Subject: [PATCH] [SVE] Don't custom lower constant predicate ISD:SPLAT_VECTOR operations. Differential Revision: https://reviews.llvm.org/D120340 --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 15 ++++++++------- llvm/lib/Target/AArch64/SVEInstrFormats.td | 13 +++++++++---- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 6848219..c181253 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -10090,13 +10090,11 @@ SDValue AArch64TargetLowering::LowerSPLAT_VECTOR(SDValue Op, case MVT::i1: { // The only legal i1 vectors are SVE vectors, so we can use SVE-specific // lowering code. - if (auto *ConstVal = dyn_cast(SplatVal)) { - // We can hande the zero case during isel. - if (ConstVal->isZero()) - return Op; - if (ConstVal->isOne()) - return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all); - } + + // We can handle the constant cases during isel. + if (isa(SplatVal)) + return Op; + // The general case of i1. There isn't any natural way to do this, // so we use some trickery with whilelo. SplatVal = DAG.getAnyExtOrTrunc(SplatVal, dl, MVT::i64); @@ -15363,6 +15361,9 @@ static bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) { return false; } + if (ISD::isConstantSplatVectorAllOnes(N.getNode())) + return true; + // "ptrue p., all" can be considered all active when is the same size // or smaller than the implicit element type represented by N. // NOTE: A larger element count implies a smaller element type. diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index b3ad395..694b0fe50 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -338,6 +338,11 @@ def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>; let Predicates = [HasSVEorStreamingSVE] in { defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>; defm PTRUES : sve_int_ptrue<0b001, "ptrues", null_frag>; + + def : Pat<(nxv16i1 immAllOnesV), (PTRUE_B 31)>; + def : Pat<(nxv8i1 immAllOnesV), (PTRUE_H 31)>; + def : Pat<(nxv4i1 immAllOnesV), (PTRUE_S 31)>; + def : Pat<(nxv2i1 immAllOnesV), (PTRUE_D 31)>; } //===----------------------------------------------------------------------===// @@ -638,10 +643,10 @@ class sve_int_pfalse opc, string asm> multiclass sve_int_pfalse opc, string asm> { def NAME : sve_int_pfalse; - def : Pat<(nxv16i1 (splat_vector (i32 0))), (!cast(NAME))>; - def : Pat<(nxv8i1 (splat_vector (i32 0))), (!cast(NAME))>; - def : Pat<(nxv4i1 (splat_vector (i32 0))), (!cast(NAME))>; - def : Pat<(nxv2i1 (splat_vector (i32 0))), (!cast(NAME))>; + def : Pat<(nxv16i1 immAllZerosV), (!cast(NAME))>; + def : Pat<(nxv8i1 immAllZerosV), (!cast(NAME))>; + def : Pat<(nxv4i1 immAllZerosV), (!cast(NAME))>; + def : Pat<(nxv2i1 immAllZerosV), (!cast(NAME))>; } class sve_int_ptest opc, string asm> -- 2.7.4