From 8c7b55724c6f9deb6d8a291cba7f932373313b57 Mon Sep 17 00:00:00 2001 From: Dylan Hung Date: Fri, 11 Nov 2022 15:30:08 +0800 Subject: [PATCH] ram: ast2600: Align the RL and WL setting Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen Signed-off-by: Dylan Hung --- arch/arm/include/asm/arch-aspeed/sdram_ast2600.h | 4 ++++ drivers/ram/aspeed/sdram_ast2600.c | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h index d2408c0..b0a91ae 100644 --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h @@ -104,6 +104,10 @@ #define SDRAM_FORCE_PRECHARGE_EN BIT(4) #define SDRAM_REFRESH_EN BIT(0) +/* MCR14 */ +#define SDRAM_WL_SETTING GENMASK(23, 20) +#define SDRAM_CL_SETTING GENMASK(19, 16) + #define SDRAM_TEST_LEN_SHIFT 4 #define SDRAM_TEST_LEN_MASK 0xfffff #define SDRAM_TEST_START_ADDR_SHIFT 24 diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index bda02d0..5d42608 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea @@ -935,6 +936,7 @@ static void ast2600_sdrammc_lock(struct dram_info *info) static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) { int i; + u32 reg; writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); @@ -969,6 +971,13 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) writel(ddr4_ac_timing[i], ®s->ac_timing[i]); + /* update CL and WL */ + reg = readl(®s->ac_timing[1]); + reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING); + reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | + FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); + writel(reg, ®s->ac_timing[1]); + writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); -- 2.7.4