From 8c649231f416551ad2a740cb4698fd9705141971 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 6 Jun 2023 18:27:33 -0700 Subject: [PATCH] [RISCV] Fix UBSan failure on signed integer overflow. --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 6bd30b2..27269be 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -211,7 +211,7 @@ static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, // constant pool. if (Seq.size() > 3) { int64_t LoVal = SignExtend64<32>(Imm); - int64_t HiVal = SignExtend64<32>((Imm - LoVal) >> 32); + int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32); if (LoVal == HiVal) { RISCVMatInt::InstSeq SeqLo = RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits()); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 90f953d..a756689 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4404,7 +4404,7 @@ static SDValue lowerConstant(SDValue Op, SelectionDAG &DAG, // that if it will avoid a constant pool. // It will require an extra temporary register though. int64_t LoVal = SignExtend64<32>(Imm); - int64_t HiVal = SignExtend64<32>((Imm - LoVal) >> 32); + int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32); if (LoVal == HiVal) { RISCVMatInt::InstSeq SeqLo = RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits()); -- 2.7.4