From 8c5fdd0575079324a9a2a5a905075db23cc6177b Mon Sep 17 00:00:00 2001 From: "bmeurer@chromium.org" Date: Mon, 3 Nov 2014 05:56:55 +0000 Subject: [PATCH] IA: Double arithmetic binops support memory operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/662813002 Patch from Weiliang Lin . Cr-Commit-Position: refs/heads/master@{#25052} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/compiler/ia32/code-generator-ia32.cc | 8 ++-- .../ia32/instruction-selector-ia32.cc | 8 ++-- src/compiler/x64/code-generator-x64.cc | 24 +++++++----- src/compiler/x64/instruction-selector-x64.cc | 8 ++-- src/ia32/assembler-ia32.cc | 38 +------------------ src/ia32/assembler-ia32.h | 11 +++--- src/x64/assembler-x64.cc | 20 ++++++++++ src/x64/assembler-x64.h | 2 + test/cctest/test-disasm-ia32.cc | 3 ++ test/cctest/test-disasm-x64.cc | 4 ++ 10 files changed, 63 insertions(+), 63 deletions(-) diff --git a/src/compiler/ia32/code-generator-ia32.cc b/src/compiler/ia32/code-generator-ia32.cc index 00444838a..fd4663653 100644 --- a/src/compiler/ia32/code-generator-ia32.cc +++ b/src/compiler/ia32/code-generator-ia32.cc @@ -314,16 +314,16 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { __ ucomisd(i.InputDoubleRegister(0), i.InputOperand(1)); break; case kSSEFloat64Add: - __ addsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + __ addsd(i.InputDoubleRegister(0), i.InputOperand(1)); break; case kSSEFloat64Sub: - __ subsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + __ subsd(i.InputDoubleRegister(0), i.InputOperand(1)); break; case kSSEFloat64Mul: - __ mulsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + __ mulsd(i.InputDoubleRegister(0), i.InputOperand(1)); break; case kSSEFloat64Div: - __ divsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + __ divsd(i.InputDoubleRegister(0), i.InputOperand(1)); break; case kSSEFloat64Mod: { // TODO(dcarney): alignment is wrong. diff --git a/src/compiler/ia32/instruction-selector-ia32.cc b/src/compiler/ia32/instruction-selector-ia32.cc index ca33ab07c..f4358eaa6 100644 --- a/src/compiler/ia32/instruction-selector-ia32.cc +++ b/src/compiler/ia32/instruction-selector-ia32.cc @@ -736,28 +736,28 @@ void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) { void InstructionSelector::VisitFloat64Add(Node* node) { IA32OperandGenerator g(this); Emit(kSSEFloat64Add, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Sub(Node* node) { IA32OperandGenerator g(this); Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Mul(Node* node) { IA32OperandGenerator g(this); Emit(kSSEFloat64Mul, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Div(Node* node) { IA32OperandGenerator g(this); Emit(kSSEFloat64Div, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } diff --git a/src/compiler/x64/code-generator-x64.cc b/src/compiler/x64/code-generator-x64.cc index 9e107e20e..b684bdf74 100644 --- a/src/compiler/x64/code-generator-x64.cc +++ b/src/compiler/x64/code-generator-x64.cc @@ -197,6 +197,16 @@ static bool HasImmediateInput(Instruction* instr, int index) { } while (0) +#define ASSEMBLE_DOUBLE_BINOP(asm_instr) \ + do { \ + if (instr->InputAt(1)->IsDoubleRegister()) { \ + __ asm_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); \ + } else { \ + __ asm_instr(i.InputDoubleRegister(0), i.InputOperand(1)); \ + } \ + } while (0) + + // Assembles an instruction after register allocation, producing machine code. void CodeGenerator::AssembleArchInstruction(Instruction* instr) { X64OperandConverter i(this, instr); @@ -346,23 +356,19 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) { ASSEMBLE_SHIFT(rorq, 6); break; case kSSEFloat64Cmp: - if (instr->InputAt(1)->IsDoubleRegister()) { - __ ucomisd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); - } else { - __ ucomisd(i.InputDoubleRegister(0), i.InputOperand(1)); - } + ASSEMBLE_DOUBLE_BINOP(ucomisd); break; case kSSEFloat64Add: - __ addsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + ASSEMBLE_DOUBLE_BINOP(addsd); break; case kSSEFloat64Sub: - __ subsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + ASSEMBLE_DOUBLE_BINOP(subsd); break; case kSSEFloat64Mul: - __ mulsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + ASSEMBLE_DOUBLE_BINOP(mulsd); break; case kSSEFloat64Div: - __ divsd(i.InputDoubleRegister(0), i.InputDoubleRegister(1)); + ASSEMBLE_DOUBLE_BINOP(divsd); break; case kSSEFloat64Mod: { __ subq(rsp, Immediate(kDoubleSize)); diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc index 17c63d2fe..f49f8bf94 100644 --- a/src/compiler/x64/instruction-selector-x64.cc +++ b/src/compiler/x64/instruction-selector-x64.cc @@ -591,28 +591,28 @@ void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) { void InstructionSelector::VisitFloat64Add(Node* node) { X64OperandGenerator g(this); Emit(kSSEFloat64Add, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Sub(Node* node) { X64OperandGenerator g(this); Emit(kSSEFloat64Sub, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Mul(Node* node) { X64OperandGenerator g(this); Emit(kSSEFloat64Mul, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } void InstructionSelector::VisitFloat64Div(Node* node) { X64OperandGenerator g(this); Emit(kSSEFloat64Div, g.DefineSameAsFirst(node), - g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); + g.UseRegister(node->InputAt(0)), g.Use(node->InputAt(1))); } diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc index aa78837bd..50c834f7c 100644 --- a/src/ia32/assembler-ia32.cc +++ b/src/ia32/assembler-ia32.cc @@ -1969,15 +1969,6 @@ void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) { } -void Assembler::addsd(XMMRegister dst, XMMRegister src) { - EnsureSpace ensure_space(this); - EMIT(0xF2); - EMIT(0x0F); - EMIT(0x58); - emit_sse_operand(dst, src); -} - - void Assembler::addsd(XMMRegister dst, const Operand& src) { EnsureSpace ensure_space(this); EMIT(0xF2); @@ -1987,15 +1978,6 @@ void Assembler::addsd(XMMRegister dst, const Operand& src) { } -void Assembler::mulsd(XMMRegister dst, XMMRegister src) { - EnsureSpace ensure_space(this); - EMIT(0xF2); - EMIT(0x0F); - EMIT(0x59); - emit_sse_operand(dst, src); -} - - void Assembler::mulsd(XMMRegister dst, const Operand& src) { EnsureSpace ensure_space(this); EMIT(0xF2); @@ -2005,15 +1987,6 @@ void Assembler::mulsd(XMMRegister dst, const Operand& src) { } -void Assembler::subsd(XMMRegister dst, XMMRegister src) { - EnsureSpace ensure_space(this); - EMIT(0xF2); - EMIT(0x0F); - EMIT(0x5C); - emit_sse_operand(dst, src); -} - - void Assembler::subsd(XMMRegister dst, const Operand& src) { EnsureSpace ensure_space(this); EMIT(0xF2); @@ -2023,7 +1996,7 @@ void Assembler::subsd(XMMRegister dst, const Operand& src) { } -void Assembler::divsd(XMMRegister dst, XMMRegister src) { +void Assembler::divsd(XMMRegister dst, const Operand& src) { EnsureSpace ensure_space(this); EMIT(0xF2); EMIT(0x0F); @@ -2097,15 +2070,6 @@ void Assembler::divps(XMMRegister dst, const Operand& src) { } -void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { - EnsureSpace ensure_space(this); - EMIT(0xF2); - EMIT(0x0F); - EMIT(0x51); - emit_sse_operand(dst, src); -} - - void Assembler::sqrtsd(XMMRegister dst, const Operand& src) { EnsureSpace ensure_space(this); EMIT(0xF2); diff --git a/src/ia32/assembler-ia32.h b/src/ia32/assembler-ia32.h index 1b1d35057..00ee95958 100644 --- a/src/ia32/assembler-ia32.h +++ b/src/ia32/assembler-ia32.h @@ -966,15 +966,16 @@ class Assembler : public AssemblerBase { void cvtsd2ss(XMMRegister dst, XMMRegister src) { cvtsd2ss(dst, Operand(src)); } - void addsd(XMMRegister dst, XMMRegister src); + void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); } void addsd(XMMRegister dst, const Operand& src); - void subsd(XMMRegister dst, XMMRegister src); + void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); } void subsd(XMMRegister dst, const Operand& src); - void mulsd(XMMRegister dst, XMMRegister src); + void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); } void mulsd(XMMRegister dst, const Operand& src); - void divsd(XMMRegister dst, XMMRegister src); + void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); } + void divsd(XMMRegister dst, const Operand& src); void xorpd(XMMRegister dst, XMMRegister src); - void sqrtsd(XMMRegister dst, XMMRegister src); + void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); } void sqrtsd(XMMRegister dst, const Operand& src); void andpd(XMMRegister dst, XMMRegister src); diff --git a/src/x64/assembler-x64.cc b/src/x64/assembler-x64.cc index 7965e771f..6e12458f9 100644 --- a/src/x64/assembler-x64.cc +++ b/src/x64/assembler-x64.cc @@ -2875,6 +2875,16 @@ void Assembler::subsd(XMMRegister dst, XMMRegister src) { } +void Assembler::subsd(XMMRegister dst, const Operand& src) { + EnsureSpace ensure_space(this); + emit(0xF2); + emit_optional_rex_32(dst, src); + emit(0x0F); + emit(0x5C); + emit_sse_operand(dst, src); +} + + void Assembler::divsd(XMMRegister dst, XMMRegister src) { EnsureSpace ensure_space(this); emit(0xF2); @@ -2885,6 +2895,16 @@ void Assembler::divsd(XMMRegister dst, XMMRegister src) { } +void Assembler::divsd(XMMRegister dst, const Operand& src) { + EnsureSpace ensure_space(this); + emit(0xF2); + emit_optional_rex_32(dst, src); + emit(0x0F); + emit(0x5E); + emit_sse_operand(dst, src); +} + + void Assembler::andpd(XMMRegister dst, XMMRegister src) { EnsureSpace ensure_space(this); emit(0x66); diff --git a/src/x64/assembler-x64.h b/src/x64/assembler-x64.h index c0467716f..d938046b1 100644 --- a/src/x64/assembler-x64.h +++ b/src/x64/assembler-x64.h @@ -1087,9 +1087,11 @@ class Assembler : public AssemblerBase { void addsd(XMMRegister dst, XMMRegister src); void addsd(XMMRegister dst, const Operand& src); void subsd(XMMRegister dst, XMMRegister src); + void subsd(XMMRegister dst, const Operand& src); void mulsd(XMMRegister dst, XMMRegister src); void mulsd(XMMRegister dst, const Operand& src); void divsd(XMMRegister dst, XMMRegister src); + void divsd(XMMRegister dst, const Operand& src); void andpd(XMMRegister dst, XMMRegister src); void orpd(XMMRegister dst, XMMRegister src); diff --git a/test/cctest/test-disasm-ia32.cc b/test/cctest/test-disasm-ia32.cc index 01628d2d6..755c9d55f 100644 --- a/test/cctest/test-disasm-ia32.cc +++ b/test/cctest/test-disasm-ia32.cc @@ -424,10 +424,13 @@ TEST(DisasmIa320) { __ movdqu(Operand(ebx, ecx, times_4, 10000), xmm0); __ addsd(xmm1, xmm0); + __ addsd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ mulsd(xmm1, xmm0); + __ mulsd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ subsd(xmm1, xmm0); __ subsd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ divsd(xmm1, xmm0); + __ divsd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ ucomisd(xmm0, xmm1); __ cmpltsd(xmm0, xmm1); diff --git a/test/cctest/test-disasm-x64.cc b/test/cctest/test-disasm-x64.cc index 004229dd4..4ae360893 100644 --- a/test/cctest/test-disasm-x64.cc +++ b/test/cctest/test-disasm-x64.cc @@ -417,9 +417,13 @@ TEST(DisasmX64) { __ movdqa(Operand(rbx, rcx, times_4, 10000), xmm0); __ addsd(xmm1, xmm0); + __ addsd(xmm1, Operand(rbx, rcx, times_4, 10000)); __ mulsd(xmm1, xmm0); + __ mulsd(xmm1, Operand(rbx, rcx, times_4, 10000)); __ subsd(xmm1, xmm0); + __ subsd(xmm1, Operand(rbx, rcx, times_4, 10000)); __ divsd(xmm1, xmm0); + __ divsd(xmm1, Operand(rbx, rcx, times_4, 10000)); __ ucomisd(xmm0, xmm1); __ andpd(xmm0, xmm1); -- 2.34.1