From 8bf9cdeaee4834bcba35322f1d84c57c691d2244 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 18 Dec 2020 10:51:17 -0500 Subject: [PATCH] AMDGPU: Use Register --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 65c7f49..939a967 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -98,7 +98,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock, if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) { for (const CalleeSavedInfo &CS : CSI) { // Insert the spill to the stack frame. - unsigned Reg = CS.getReg(); + MCRegister Reg = CS.getReg(); MachineInstrSpan MIS(I, &SaveBlock); const TargetRegisterClass *RC = @@ -217,7 +217,8 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) { const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs(); for (unsigned I = 0; CSRegs[I]; ++I) { - unsigned Reg = CSRegs[I]; + MCRegister Reg = CSRegs[I]; + if (SavedRegs.test(Reg)) { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, MVT::i32); -- 2.7.4