From 8bde5f06a11d2ed30cc14b4960548d8da7a167b8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 6 Jun 2021 12:48:25 -0700 Subject: [PATCH] [RISCV] Replace && with ||. Spotted by coverity. We should be exiting when the shift amount is greater than the bit width regardless of whether it is a power of 2. Reported by Simon Pilgrim here https://reviews.llvm.org/D96661 This requires getting a shift amount that is out of bounds that wasn't already optimized by SelectionDAG. This would be pretty trick to construct a test for. Or it would require a non-power of 2 shift amount and a mask that has runs of ones and zeros of the next lowest power of 2 from that shift amount. I tried a little to produce a test for this, but didn't get it to work. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 87c4689..0b2c79b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5122,7 +5122,7 @@ matchRISCVBitmanipPat(SDValue Op, ArrayRef BitmanipMasks) { uint64_t ShAmt = Op.getConstantOperandVal(1); unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; - if (ShAmt >= Width && !isPowerOf2_64(ShAmt)) + if (ShAmt >= Width || !isPowerOf2_64(ShAmt)) return None; // If we don't have enough masks for 64 bit, then we must be trying to // match SHFL so we're only allowed to shift 1/4 of the width. -- 2.7.4