From 8bce21c154fa363b3d8ae0d8fdba4ffec6931df4 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 26 Jul 2013 20:51:20 +0000 Subject: [PATCH] [mips] Fix FP conditional move instructions to have explicit FP condition code register operands. llvm-svn: 187242 --- llvm/lib/Target/Mips/MipsCondMov.td | 14 ++++++-------- llvm/lib/Target/Mips/MipsISelLowering.cpp | 3 ++- llvm/lib/Target/Mips/MipsInstrFPU.td | 4 ++-- llvm/lib/Target/Mips/MipsInstrFormats.td | 6 ++++-- llvm/test/MC/Disassembler/Mips/mips32.txt | 18 ++++++++++++++++++ llvm/test/MC/Disassembler/Mips/mips32_le.txt | 18 ++++++++++++++++++ 6 files changed, 50 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td index 8f5c4dcb..607c2a9 100644 --- a/llvm/lib/Target/Mips/MipsCondMov.td +++ b/llvm/lib/Target/Mips/MipsCondMov.td @@ -34,20 +34,18 @@ class CMov_I_F_FT : - InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F), - !strconcat(opstr, "\t$rd, $rs, $$fcc0"), - [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> { - let Uses = [FCC0]; + InstSE<(outs RC:$rd), (ins RC:$rs, FCC:$fcc, RC:$F), + !strconcat(opstr, "\t$rd, $rs, $fcc"), + [(set RC:$rd, (OpNode RC:$rs, FCC:$fcc, RC:$F))], Itin, FrmFR> { let Constraints = "$F = $rd"; } // cond:float, data:float class CMov_F_F_FT : - InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F), - !strconcat(opstr, "\t$fd, $fs, $$fcc0"), - [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> { - let Uses = [FCC0]; + InstSE<(outs RC:$fd), (ins RC:$fs, FCC:$fcc, RC:$F), + !strconcat(opstr, "\t$fd, $fs, $fcc"), + [(set RC:$fd, (OpNode RC:$fs, FCC:$fcc, RC:$F))], Itin, FrmFR> { let Constraints = "$F = $fd"; } diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 10efc8a..8bf4249 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -519,9 +519,10 @@ static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, SDLoc DL) { ConstantSDNode *CC = cast(Cond.getOperand(2)); bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); + SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, - True.getValueType(), True, False, Cond); + True.getValueType(), True, FCC0, False, Cond); } static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 3975de0..ce68a28 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -29,8 +29,8 @@ def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisVT<2, OtherVT>]>; def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, SDTCisVT<2, i32>]>; -def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, - SDTCisSameAs<1, 2>]>; +def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, + SDTCisSameAs<1, 3>]>; def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 61b01c0..fb55cd2 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -716,12 +716,13 @@ class CMov_I_F_FM funct, bits<5> fmt> { class CMov_F_I_FM { bits<5> rd; bits<5> rs; + bits<3> fcc; bits<32> Inst; let Inst{31-26} = 0; let Inst{25-21} = rs; - let Inst{20-18} = 0; // cc + let Inst{20-18} = fcc; let Inst{17} = 0; let Inst{16} = tf; let Inst{15-11} = rd; @@ -732,12 +733,13 @@ class CMov_F_I_FM { class CMov_F_F_FM fmt, bit tf> { bits<5> fd; bits<5> fs; + bits<3> fcc; bits<32> Inst; let Inst{31-26} = 0x11; let Inst{25-21} = fmt; - let Inst{20-18} = 0; // cc + let Inst{20-18} = fcc; let Inst{17} = 0; let Inst{16} = tf; let Inst{15-11} = fs; diff --git a/llvm/test/MC/Disassembler/Mips/mips32.txt b/llvm/test/MC/Disassembler/Mips/mips32.txt index d624889..6d02925 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32.txt @@ -266,6 +266,24 @@ # CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 +# CHECK: movf $3, $2, $fcc7 +0x00,0x5c,0x18,0x01 + +# CHECK: movf.d $f4, $f2, $fcc7 +0x46,0x3c,0x11,0x11 + +# CHECK: movf.s $f4, $f2, $fcc7 +0x46,0x1c,0x11,0x11 + +# CHECK: movt $3, $2, $fcc7 +0x00,0x5d,0x18,0x01 + +# CHECK: movt.d $f4, $f2, $fcc7 +0x46,0x3d,0x11,0x11 + +# CHECK: movt.s $f4, $f2, $fcc7 +0x46,0x1d,0x11,0x11 + # CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 diff --git a/llvm/test/MC/Disassembler/Mips/mips32_le.txt b/llvm/test/MC/Disassembler/Mips/mips32_le.txt index 52cf6eb..61e6fc8 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32_le.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32_le.txt @@ -272,6 +272,24 @@ # CHECK: move $3, $2 0x25,0x18,0x40,0x00 +# CHECK: movf $3, $2, $fcc7 +0x01,0x18,0x5c,0x00 + +# CHECK: movf.d $f4, $f2, $fcc7 +0x11,0x11,0x3c,0x46 + +# CHECK: movf.s $f4, $f2, $fcc7 +0x11,0x11,0x1c,0x46 + +# CHECK: movt $3, $2, $fcc7 +0x01,0x18,0x5d,0x00 + +# CHECK: movt.d $f4, $f2, $fcc7 +0x11,0x11,0x3d,0x46 + +# CHECK: movt.s $f4, $f2, $fcc7 +0x11,0x11,0x1d,0x46 + # CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 -- 2.7.4