From 8aed3cb3f46fe8fec3ba1a60d40bfefec6e11c08 Mon Sep 17 00:00:00 2001 From: rsandifo Date: Fri, 12 Jan 2007 09:32:59 +0000 Subject: [PATCH] gcc/ 200x-xx-xx Julian Brown Nathan Sidwell Richard Sandiford * config.gcc (m680[012]0-*-*, m68k*-*-*): Set m68k_cpu_ident to the -mcpu= argument associated with the --with-cpu setting. Define M68K_DEFAULT_TUNE to the default -mtune= option, if different from the one implied by the -mcpu setting. Accept --with-cpu=FOO if FOO is listed in m68k-devices.def, using mcpu=FOO as the default CPU option. Set target_cpu_default2. * doc/invoke.texi: Mention ColdFire in the introduction to the m68k options. Document the new -march, -mcpu, -mtune, -mdiv, -mno-div and -mhard-float options. Make -m68881 a synonym for -mhard-float. Document the previously-undocumented -m5206e, -m528x, -m5307 and -m5407 options. Tweak the existing option documentation for consistency. * doc/install.texi: Mention new --with-cpu arguments. * config/m68k/m68k.h (OPTION_DEFAULT_SPECS): Only use the default CPU if neither -mcpu nor -march are specified. (ASM_CPU_SPEC): Pass down -mcpu and -march options. (TARGET_CPU_CPP_BUILTINS): Set __mcfisa*__ macros from TARGET_ISA*. Set the legacy __mcf*__ cpu macros in the same way, using m68k_tune to decide between families that implement the same ISA. Use m68k_tune to set __mcfv4e__. (FL_BITFIELD, FL_68881, FL_COLDFIRE, FL_CF_HWDIV, FL_CF_MAC) (FL_CF_EMAC, FL_CF_EMAC_B, FL_CF_USP, FL_CF_FPU, FL_ISA_68000) (FL_ISA_68010, FL_ISA_68020, FL_ISA_68040, FL_ISA_A, FL_ISA_B) (FL_ISA_C, FL_ISA_MMU): New macros. (MASK_COLDFIRE): Delete. (TARGET_68010, TARGET_68020, TARGET_68040_ONLY, TARGET_COLDFIRE) (TARGET_ISAB): Redefine in terms of m68k_cpu_flags. (TARGET_68881, TARGET_COLDFIRE_FPU): Redefine in terms of m68k_fpu. (TARGET_HARD_FLOAT): Do not define here. (TARGET_ISAAPLUS, TARGET_ISAC): New macros. (TUNE_68000): New macro. (TUNE_68000_10): Redefine in terms of TUNE_68000 and TUNE_68010. (TUNE_68010, TUNE_68030, TUNE_68040, TUNE_68060, TUNE_CPU32) (TUNE_CFV2): Redefine in terms of m68k_tune. (uarch_type, target_device, fpu_type): New enums. (m68k_cpu, m68k_tune, m68k_fpu, m68k_cpu_flags): Declare. * config/m68k/m68k.c (TARGET_DEFAULT): Remove MASK_68881. (FL_FOR_isa_00, FL_FOR_isa_10, FL_FOR_isa_20, FL_FOR_isa_40) (FL_FOR_isa_cpu32, FL_FOR_isa_a, FL_FOR_isa_aplus, FL_FOR_isa_b) (FL_FOR_isa_c): New macros. (m68k_isa): New enum. (m68k_target_selection): New structure. (all_devices, all_isas, all_microarchs): New tables. (m68k_cpu_entry, m68k_arch_entry, m68k_tune_entry, m68k_cpu) (m68k_tune, m68k_fpu, m68k_cpu_flags): New variables. (MASK_ALL_CPU_BITS): Delete. (m68k_find_selection): New function. (m68k_handle_option): Handle -mcpu=, -march= and -mtune=. Map the legacy target options to a combination of the new ones. (override_options): Set m68k_cpu, m68k_tune, m68k_fpu and m68k_cpu_flags. Handle M68K_DEFAULT_TUNE. Use m68k_cpu_flags to derive default MASK_BITFIELD, MASK_CF_HWDIV and MASK_HARD_FLOAT settings. * config/m68k/m68k.opt (m5200, m5206e, m528x, m5307, m5407, mcfv4e) (m68010, m68020, m68020-40, m68020-60, m68030, m68040): Remove Mask properties. (m68881, msoft-float): Change mask from 68881 to HARD_FLOAT. (march=, mcpu=, mdiv, mhard-float, mtune=): New options. * config/m68k/m68k-devices.def: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@120713 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 64 +++++++++ gcc/config.gcc | 29 +++- gcc/config/m68k/m68k-devices.def | 144 +++++++++++++++++++ gcc/config/m68k/m68k.c | 293 +++++++++++++++++++++++++++++++-------- gcc/config/m68k/m68k.h | 167 ++++++++++++++++------ gcc/config/m68k/m68k.opt | 48 +++++-- gcc/doc/install.texi | 6 +- gcc/doc/invoke.texi | 172 +++++++++++++++++++---- 8 files changed, 777 insertions(+), 146 deletions(-) create mode 100644 gcc/config/m68k/m68k-devices.def diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e7ea8d5..6f6508e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,67 @@ +2007-01-12 Julian Brown + Nathan Sidwell + Richard Sandiford + + * config.gcc (m680[012]0-*-*, m68k*-*-*): Set m68k_cpu_ident to + the -mcpu= argument associated with the --with-cpu setting. + Define M68K_DEFAULT_TUNE to the default -mtune= option, + if different from the one implied by the -mcpu setting. + Accept --with-cpu=FOO if FOO is listed in m68k-devices.def, + using mcpu=FOO as the default CPU option. Set target_cpu_default2. + * doc/invoke.texi: Mention ColdFire in the introduction to the + m68k options. Document the new -march, -mcpu, -mtune, -mdiv, + -mno-div and -mhard-float options. Make -m68881 a synonym for + -mhard-float. Document the previously-undocumented -m5206e, + -m528x, -m5307 and -m5407 options. Tweak the existing option + documentation for consistency. + * doc/install.texi: Mention new --with-cpu arguments. + * config/m68k/m68k.h (OPTION_DEFAULT_SPECS): Only use the + default CPU if neither -mcpu nor -march are specified. + (ASM_CPU_SPEC): Pass down -mcpu and -march options. + (TARGET_CPU_CPP_BUILTINS): Set __mcfisa*__ macros from + TARGET_ISA*. Set the legacy __mcf*__ cpu macros in the same way, + using m68k_tune to decide between families that implement the + same ISA. Use m68k_tune to set __mcfv4e__. + (FL_BITFIELD, FL_68881, FL_COLDFIRE, FL_CF_HWDIV, FL_CF_MAC) + (FL_CF_EMAC, FL_CF_EMAC_B, FL_CF_USP, FL_CF_FPU, FL_ISA_68000) + (FL_ISA_68010, FL_ISA_68020, FL_ISA_68040, FL_ISA_A, FL_ISA_B) + (FL_ISA_C, FL_ISA_MMU): New macros. + (MASK_COLDFIRE): Delete. + (TARGET_68010, TARGET_68020, TARGET_68040_ONLY, TARGET_COLDFIRE) + (TARGET_ISAB): Redefine in terms of m68k_cpu_flags. + (TARGET_68881, TARGET_COLDFIRE_FPU): Redefine in terms of m68k_fpu. + (TARGET_HARD_FLOAT): Do not define here. + (TARGET_ISAAPLUS, TARGET_ISAC): New macros. + (TUNE_68000): New macro. + (TUNE_68000_10): Redefine in terms of TUNE_68000 and TUNE_68010. + (TUNE_68010, TUNE_68030, TUNE_68040, TUNE_68060, TUNE_CPU32) + (TUNE_CFV2): Redefine in terms of m68k_tune. + (uarch_type, target_device, fpu_type): New enums. + (m68k_cpu, m68k_tune, m68k_fpu, m68k_cpu_flags): Declare. + * config/m68k/m68k.c (TARGET_DEFAULT): Remove MASK_68881. + (FL_FOR_isa_00, FL_FOR_isa_10, FL_FOR_isa_20, FL_FOR_isa_40) + (FL_FOR_isa_cpu32, FL_FOR_isa_a, FL_FOR_isa_aplus, FL_FOR_isa_b) + (FL_FOR_isa_c): New macros. + (m68k_isa): New enum. + (m68k_target_selection): New structure. + (all_devices, all_isas, all_microarchs): New tables. + (m68k_cpu_entry, m68k_arch_entry, m68k_tune_entry, m68k_cpu) + (m68k_tune, m68k_fpu, m68k_cpu_flags): New variables. + (MASK_ALL_CPU_BITS): Delete. + (m68k_find_selection): New function. + (m68k_handle_option): Handle -mcpu=, -march= and -mtune=. + Map the legacy target options to a combination of the new ones. + (override_options): Set m68k_cpu, m68k_tune, m68k_fpu and + m68k_cpu_flags. Handle M68K_DEFAULT_TUNE. Use m68k_cpu_flags + to derive default MASK_BITFIELD, MASK_CF_HWDIV and MASK_HARD_FLOAT + settings. + * config/m68k/m68k.opt (m5200, m5206e, m528x, m5307, m5407, mcfv4e) + (m68010, m68020, m68020-40, m68020-60, m68030, m68040): Remove Mask + properties. + (m68881, msoft-float): Change mask from 68881 to HARD_FLOAT. + (march=, mcpu=, mdiv, mhard-float, mtune=): New options. + * config/m68k/m68k-devices.def: New file. + 2007-01-12 Richard Sandiford Nathan Sidwell diff --git a/gcc/config.gcc b/gcc/config.gcc index 17a69dc..5aa991c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2784,13 +2784,28 @@ case "${target}" in # We always have a $with_cpu setting here. case "$with_cpu" in - "m68000" | "m68010" | "m68020" | "m68030" | "m68040" | "m68060" | "m68020-40" | "m68020-60") - # OK + "m68000" | "m68010" | "m68020" | "m68030" | "m68040" | "m68060") + m68k_cpu_ident=$with_cpu + ;; + "m68020-40") + m68k_cpu_ident=m68020 + tm_defines="$tm_defines M68K_DEFAULT_TUNE=u68020_40" + ;; + "m68020-60") + m68k_cpu_ident=m68020 + tm_defines="$tm_defines M68K_DEFAULT_TUNE=u68020_60" ;; *) - echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 - echo "m68000 m68010 m68020 m68030 m68040 m68060 m68020-40 m68020-60" 1>&2 - exit 1 + # We need the C identifier rather than the string. + m68k_cpu_ident=`awk -v arg="\"$with_cpu\"" \ + 'BEGIN { FS="[ \t]*[,()][ \t]*" }; \ + $1 == "M68K_DEVICE" && $2 == arg { print $3 }' \ + ${srcdir}/config/m68k/m68k-devices.def` + if [ x"$m68k_cpu_ident" = x ] ; then + echo "Unknown CPU used in --with-cpu=$with_cpu" 1>&2 + exit 1 + fi + with_cpu="mcpu=$with_cpu" ;; esac ;; @@ -3049,6 +3064,10 @@ case ${target} in fi ;; + m680[012]0-*-* | m68k*-*-*) + target_cpu_default2=$m68k_cpu_ident + ;; + mips*-*-*) if test x$gnu_ld = xyes then diff --git a/gcc/config/m68k/m68k-devices.def b/gcc/config/m68k/m68k-devices.def new file mode 100644 index 0000000..f779302 --- /dev/null +++ b/gcc/config/m68k/m68k-devices.def @@ -0,0 +1,144 @@ +/* m68k device names -*- C -*- + Copyright (C) 2005, 2006 Free Software Foundation, Inc. + Written by CodeSourcery + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* This file lists each target device that we support. It is used by + both C code and build scripts. + + Following Freescale's lead, we group devices into families that share + the same core and extension units. Devices in these families differ + only in the set of peripherals they provide. We pick one device to + act as the representative of each family. + + We further group device families into multilibs, again picking one + family (and its representative device) to represent each multilib. + + Devices are declared using the construct: + + M68K_DEVICE (NAME, ENUM_VALUE, FAMILY, MULTILIB, MICROARCH, ISA, FLAGS) + + where the arguments are as follows: + + NAME + The name of the device as a string. This string acts as the + device's -mcpu argument and is guaranteed to be unique. + + ENUM_VALUE + The associated value in the target_device enumeration. + This value is also guaranteed to be unique. + + FAMILY + The NAME field of the family's representative device. + + MULTILIB + The NAME field of the multilib's representative device. + + MICROARCH + The class of core used by devices in this family. The field + is a uarch enumeration value without the leading "u". + + ISA + The ISA implemented by this family. The field is + an m68k_isa enumeration value. + + FLAGS + The FL_* flags that apply to this family, excluding FL_FOR_isa_*. + See m68k.h for the full list. + + There is a bit of duplication between devices in the same family, + but this approach makes scripting easier. We keep each entry on + a single line for the same reason. */ + +/* 680x0 series processors. */ +M68K_DEVICE ("68000", m68000, "68000", "68000", 68000, isa_00, 0) +M68K_DEVICE ("68010", m68010, "68010", "68000", 68010, isa_10, 0) +M68K_DEVICE ("68020", m68020, "68020", "68020", 68020, isa_20, FL_MMU) +M68K_DEVICE ("68030", m68030, "68030", "68020", 68030, isa_20, FL_MMU) +M68K_DEVICE ("68040", m68040, "68040", "68040", 68040, isa_40, FL_MMU) +M68K_DEVICE ("68060", m68060, "68060", "68060", 68060, isa_40, FL_MMU) +M68K_DEVICE ("68302", m68302, "68302", "68000", 68000, isa_00, FL_MMU) +M68K_DEVICE ("68332", m68332, "68332", "cpu32", cpu32, isa_cpu32, FL_MMU) +M68K_DEVICE ("cpu32", cpu32, "cpu32", "cpu32", cpu32, isa_cpu32, FL_MMU) + +/* ColdFire CFV2 processors. */ +M68K_DEVICE ("5202", mcf5202, "5206", "5206", cfv2, isa_a, 0) +M68K_DEVICE ("5204", mcf5204, "5206", "5206", cfv2, isa_a, 0) +M68K_DEVICE ("5206", mcf5206, "5206", "5206", cfv2, isa_a, 0) +M68K_DEVICE ("5206e", mcf5206e, "5206e", "5206e", cfv2, isa_a, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5207", mcf5207, "5208", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5208", mcf5208, "5208", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5210a", mcf5210a, "5211a", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5211a", mcf5211a, "5211a", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5211", mcf5211, "5213", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5212", mcf5212, "5213", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5213", mcf5213, "5213", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5214", mcf5214, "5216", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5216", mcf5216, "5216", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52230", mcf52230, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52231", mcf52231, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52232", mcf52232, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52233", mcf52233, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52234", mcf52234, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("52235", mcf52235, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5224", mcf5224, "5225", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5225", mcf5225, "5225", "5213", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5232", mcf5232, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5233", mcf5233, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5234", mcf5234, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5235", mcf5235, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("523x", mcf523x, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5249", mcf5249, "5249", "5249", cfv2, isa_a, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5250", mcf5250, "5250", "5249", cfv2, isa_a, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5270", mcf5270, "5271", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5271", mcf5271, "5271", "5208", cfv2, isa_aplus, FL_CF_HWDIV) +M68K_DEVICE ("5272", mcf5272, "5272", "5206e", cfv2, isa_a, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5274", mcf5274, "5275", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5275", mcf5275, "5275", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5280", mcf5280, "5282", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5281", mcf5281, "5282", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5282", mcf5282, "5282", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("528x", mcf528x, "5282", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) + +/* CFV3 processors. */ +M68K_DEVICE ("5307", mcf5307, "5307", "5307", cfv3, isa_a, FL_CF_HWDIV | FL_CF_MAC) +M68K_DEVICE ("5327", mcf5327, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5328", mcf5328, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5329", mcf5329, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("532x", mcf532x, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5372", mcf5372, "5373", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("5373", mcf5373, "5373", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) +M68K_DEVICE ("537x", mcf537x, "5373", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC) + +/* CFV4/CFV4e processors. */ +M68K_DEVICE ("5407", mcf5407, "5407", "5407", cfv4, isa_b, FL_CF_MAC) +M68K_DEVICE ("5470", mcf5470, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5471", mcf5471, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5472", mcf5472, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5473", mcf5473, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5474", mcf5474, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5475", mcf5475, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("547x", mcf547x, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5480", mcf5480, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5481", mcf5481, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5482", mcf5482, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5483", mcf5483, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5484", mcf5484, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("5485", mcf5485, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) +M68K_DEVICE ("548x", mcf548x, "5485", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU) diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 81ad31b..74c439d 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -176,7 +176,7 @@ int m68k_last_compare_had_fp_operands; #define TARGET_ASM_FILE_START_APP_OFF true #undef TARGET_DEFAULT_TARGET_FLAGS -#define TARGET_DEFAULT_TARGET_FLAGS (MASK_STRICT_ALIGNMENT|MASK_68881) +#define TARGET_DEFAULT_TARGET_FLAGS MASK_STRICT_ALIGNMENT #undef TARGET_HANDLE_OPTION #define TARGET_HANDLE_OPTION m68k_handle_option @@ -201,12 +201,152 @@ static const struct attribute_spec m68k_attribute_table[] = struct gcc_target targetm = TARGET_INITIALIZER; -/* These bits are controlled by all CPU selection options. Many options - also control MASK_68881, but some (notably -m68020) leave it alone. */ +/* Base flags for 68k ISAs. */ +#define FL_FOR_isa_00 FL_ISA_68000 +#define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) +/* FL_68881 controls the default setting of -m68881. gcc has traditionally + generated 68881 code for 68020 and 68030 targets unless explicitly told + not to. */ +#define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ + | FL_BITFIELD | FL_68881) +#define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) +#define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) + +/* Base flags for ColdFire ISAs. */ +#define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) +#define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) +/* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ +#define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) +#define FL_FOR_isa_c (FL_FOR_isa_b | FL_ISA_C | FL_CF_USP) + +enum m68k_isa +{ + /* Traditional 68000 instruction sets. */ + isa_00, + isa_10, + isa_20, + isa_40, + isa_cpu32, + /* ColdFire instruction set variants. */ + isa_a, + isa_aplus, + isa_b, + isa_c, + isa_max +}; + +/* Information about one of the -march, -mcpu or -mtune arguments. */ +struct m68k_target_selection +{ + /* The argument being described. */ + const char *name; + + /* For -mcpu, this is the device selected by the option. + For -mtune and -march, it is a representative device + for the microarchitecture or ISA respectively. */ + enum target_device device; + + /* The M68K_DEVICE fields associated with DEVICE. See the comment + in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ + const char *family; + enum uarch_type microarch; + enum m68k_isa isa; + unsigned long flags; +}; + +/* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ +static const struct m68k_target_selection all_devices[] = +{ +#define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ + { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, +#include "m68k-devices.def" +#undef M68K_DEVICE + { NULL, unk_device, NULL, unk_arch, isa_max, 0 } +}; + +/* A list of all ISAs, mapping each one to a representative device. + Used for -march selection. */ +static const struct m68k_target_selection all_isas[] = +{ + { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, + { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, + { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, + { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, + { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, + { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, + { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, + { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a + | FL_CF_HWDIV) }, + { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus + | FL_CF_HWDIV) }, + { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, + { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c + | FL_CF_FPU + | FL_CF_EMAC) }, + { NULL, unk_device, NULL, unk_arch, isa_max, 0 } +}; + +/* A list of all microarchitectures, mapping each one to a representative + device. Used for -mtune selection. */ +static const struct m68k_target_selection all_microarchs[] = +{ + { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 }, + { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 }, + { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 }, + { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 }, + { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 }, + { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 }, + { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 }, + { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 }, + { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 }, + { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a }, + { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a + | FL_CF_HWDIV) }, + { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b }, + { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b + | FL_CF_USP + | FL_CF_EMAC + | FL_CF_FPU) }, + { NULL, unk_device, NULL, unk_arch, isa_max, 0 } +}; + +/* The entries associated with the -mcpu, -march and -mtune settings, + or null for options that have not been used. */ +const struct m68k_target_selection *m68k_cpu_entry; +const struct m68k_target_selection *m68k_arch_entry; +const struct m68k_target_selection *m68k_tune_entry; -#define MASK_ALL_CPU_BITS \ - (MASK_COLDFIRE | MASK_CF_HWDIV | MASK_68060 | MASK_68040 \ - | MASK_68040_ONLY | MASK_68030 | MASK_68020 | MASK_68010 | MASK_BITFIELD) +/* Which CPU we are generating code for. */ +enum target_device m68k_cpu; + +/* Which microarchitecture to tune for. */ +enum uarch_type m68k_tune; + +/* Which FPU to use. */ +enum fpu_type m68k_fpu; + +/* The set of FL_* flags that apply to the target processor. */ +unsigned int m68k_cpu_flags; + +/* See whether TABLE has an entry with name NAME. Return true and + store the entry in *ENTRY if so, otherwise return false and + leave *ENTRY alone. */ + +static bool +m68k_find_selection (const struct m68k_target_selection **entry, + const struct m68k_target_selection *table, + const char *name) +{ + size_t i; + + for (i = 0; table[i].name; i++) + if (strcmp (table[i].name, name) == 0) + { + *entry = table + i; + return true; + } + return false; +} /* Implement TARGET_HANDLE_OPTION. */ @@ -215,90 +355,69 @@ m68k_handle_option (size_t code, const char *arg, int value) { switch (code) { + case OPT_march_: + return m68k_find_selection (&m68k_arch_entry, all_isas, arg); + + case OPT_mcpu_: + return m68k_find_selection (&m68k_cpu_entry, all_devices, arg); + + case OPT_mtune_: + return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg); + case OPT_m5200: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_5200; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206"); case OPT_m5206e: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_5200 | MASK_CF_HWDIV; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e"); case OPT_m528x: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_528x | MASK_CF_HWDIV; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x"); case OPT_m5307: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_CFV3 | MASK_CF_HWDIV; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307"); case OPT_m5407: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_CFV4 | MASK_CF_HWDIV; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407"); case OPT_mcfv4e: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_CFV4 | MASK_CF_HWDIV | MASK_CFV4E; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x"); case OPT_m68000: case OPT_mc68000: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000"); case OPT_m68010: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_68010; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010"); case OPT_m68020: case OPT_mc68020: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= MASK_68010 | MASK_68020 | MASK_BITFIELD; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"); case OPT_m68020_40: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= (MASK_BITFIELD | MASK_68881 | MASK_68010 - | MASK_68020 | MASK_68040); - return true; + return (m68k_find_selection (&m68k_tune_entry, all_microarchs, + "68020-40") + && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); case OPT_m68020_60: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= (MASK_BITFIELD | MASK_68881 | MASK_68010 - | MASK_68020 | MASK_68040 | MASK_68060); - return true; + return (m68k_find_selection (&m68k_tune_entry, all_microarchs, + "68020-60") + && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020")); case OPT_m68030: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= MASK_68010 | MASK_68020 | MASK_68030 | MASK_BITFIELD; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030"); case OPT_m68040: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= (MASK_68010 | MASK_68020 | MASK_68881 | MASK_BITFIELD - | MASK_68040_ONLY | MASK_68040); - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040"); case OPT_m68060: - target_flags &= ~MASK_ALL_CPU_BITS; - target_flags |= (MASK_68010 | MASK_68020 | MASK_68881 | MASK_BITFIELD - | MASK_68040_ONLY | MASK_68060); - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060"); case OPT_m68302: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302"); case OPT_m68332: case OPT_mcpu32: - target_flags &= ~(MASK_ALL_CPU_BITS | MASK_68881); - target_flags |= MASK_68010 | MASK_68020; - return true; + return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332"); case OPT_mshared_library_id_: if (value > MAX_LIBRARY_ID) @@ -325,6 +444,68 @@ m68k_handle_option (size_t code, const char *arg, int value) void override_options (void) { + const struct m68k_target_selection *entry; + unsigned long target_mask; + + /* User can choose: + + -mcpu= + -march= + -mtune= + + -march=ARCH should generate code that runs any processor + implementing architecture ARCH. -mcpu=CPU should override -march + and should generate code that runs on processor CPU, making free + use of any instructions that CPU understands. -mtune=UARCH applies + on top of -mcpu or -march and optimises the code for UARCH. It does + not change the target architecture. */ + if (m68k_cpu_entry) + { + /* Complain if the -march setting is for a different microarchitecture, + or includes flags that the -mcpu setting doesn't. */ + if (m68k_arch_entry + && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch + || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) + warning (0, "-mcpu=%s conflicts with -march=%s", + m68k_cpu_entry->name, m68k_arch_entry->name); + + entry = m68k_cpu_entry; + } + else + entry = m68k_arch_entry; + + if (!entry) + entry = all_devices + TARGET_CPU_DEFAULT; + + m68k_cpu_flags = entry->flags; + + /* Use the architecture setting to derive default values for + certain flags. */ + target_mask = 0; + if ((m68k_cpu_flags & FL_BITFIELD) != 0) + target_mask |= MASK_BITFIELD; + if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) + target_mask |= MASK_CF_HWDIV; + if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) + target_mask |= MASK_HARD_FLOAT; + target_flags |= target_mask & ~target_flags_explicit; + + /* Set the directly-usable versions of the -mcpu and -mtune settings. */ + m68k_cpu = entry->device; + if (m68k_tune_entry) + m68k_tune = m68k_tune_entry->microarch; +#ifdef M68K_DEFAULT_TUNE + else if (!m68k_cpu_entry && !m68k_arch_entry) + m68k_tune = M68K_DEFAULT_TUNE; +#endif + else + m68k_tune = entry->microarch; + + /* Set the type of FPU. */ + m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE + : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE + : FPUTYPE_68881); + /* Sanity check to ensure that msep-data and mid-sahred-library are not * both specified together. Doing so simply doesn't make sense. */ diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index de8e27c..7ef17ba 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -37,7 +37,7 @@ Boston, MA 02110-1301, USA. */ { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\ %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\ %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\ --%(VALUE)}}}}}}}}}}}}}}}}}}}" }, +%{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" }, /* Pass flags to gas indicating which type of processor we have. This can be simplified when we can rely on the assembler supporting .cpu @@ -48,6 +48,7 @@ Boston, MA 02110-1301, USA. */ %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\ %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\ %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\ +%{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ " #define ASM_SPEC "%(asm_cpu_spec)" @@ -100,30 +101,50 @@ Boston, MA 02110-1301, USA. */ builtin_define_std ("mcpu32"); \ } \ if (TARGET_COLDFIRE) \ - builtin_define ("__mcoldfire__"); \ - if (TARGET_5200) \ - builtin_define ("__mcf5200__"); \ - if (TARGET_528x) \ { \ - builtin_define ("__mcf528x__"); \ - builtin_define ("__mcf5200__"); \ - } \ - if (TARGET_CFV3) \ - { \ - builtin_define ("__mcf5300__"); \ - builtin_define ("__mcf5307__"); \ - } \ - if (TARGET_CFV4) \ - { \ - builtin_define ("__mcf5400__"); \ - builtin_define ("__mcf5407__"); \ - } \ - if (TARGET_CFV4E) \ - { \ - builtin_define ("__mcfv4e__"); \ + builtin_define ("__mcoldfire__"); \ + if (TARGET_ISAC) \ + builtin_define ("__mcfisac__"); \ + else if (TARGET_ISAB) \ + { \ + builtin_define ("__mcfisab__"); \ + /* ISA_B: Legacy 5407 defines. */ \ + builtin_define ("__mcf5400__"); \ + builtin_define ("__mcf5407__"); \ + } \ + else if (TARGET_ISAAPLUS) \ + { \ + builtin_define ("__mcfisaaplus__"); \ + /* ISA_A+: legacy defines. */ \ + builtin_define ("__mcf528x__"); \ + builtin_define ("__mcf5200__"); \ + } \ + else \ + { \ + builtin_define ("__mcfisaa__"); \ + /* ISA_A: legacy defines. */ \ + switch (m68k_tune) \ + { \ + case ucfv2: \ + builtin_define ("__mcf5200__"); \ + break; \ + \ + case ucfv3: \ + builtin_define ("__mcf5307__"); \ + builtin_define ("__mcf5300__"); \ + break; \ + \ + default: \ + break; \ + } \ + } \ + if (m68k_tune == ucfv4e) \ + builtin_define ("__mcfv4e__"); \ } \ + \ if (TARGET_CF_HWDIV) \ builtin_define ("__mcfhwdiv__"); \ + \ builtin_assert ("cpu=m68k"); \ builtin_assert ("machine=m68k"); \ } \ @@ -139,30 +160,53 @@ Boston, MA 02110-1301, USA. */ /* Set the default. */ #define INT_OP_GROUP INT_OP_DOT_WORD -/* Compile for a CPU32. A 68020 without bitfields is a good - heuristic for a CPU32. */ -#define TUNE_CPU32 (TARGET_68020 && !TARGET_BITFIELD) - -/* Is the target a ColdFire? */ -#define MASK_COLDFIRE \ - (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4 | MASK_CFV4E) -#define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0) +/* Bit values used by m68k-devices.def to identify processor capabilities. */ +#define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ +#define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ +#define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ +#define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ +#define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ +#define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ +#define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ +#define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ +#define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ +#define FL_ISA_68000 (1 << 9) +#define FL_ISA_68010 (1 << 10) +#define FL_ISA_68020 (1 << 11) +#define FL_ISA_68040 (1 << 12) +#define FL_ISA_A (1 << 13) +#define FL_ISA_APLUS (1 << 14) +#define FL_ISA_B (1 << 15) +#define FL_ISA_C (1 << 16) +#define FL_MMU 0 /* Used by multilib machinery. */ + +#define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) +#define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) +#define TARGET_68040_ONLY ((m68k_cpu_flags & FL_ISA_68040) != 0) +#define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) +#define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) +#define TARGET_68881 (m68k_fpu == FPUTYPE_68881) -#define TARGET_COLDFIRE_FPU TARGET_CFV4E - -#define TARGET_HARD_FLOAT (TARGET_68881 || TARGET_COLDFIRE_FPU) /* Size (in bytes) of FPU registers. */ #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) -#define TARGET_ISAB TARGET_CFV4 - -#define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE) -#define TUNE_68010 TARGET_68010 -#define TUNE_68030 TARGET_68030 -#define TUNE_68040 TARGET_68040 -#define TUNE_68060 TARGET_68060 +#define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) +#define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) +#define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) + +#define TUNE_68000 (m68k_tune == u68000) +#define TUNE_68010 (m68k_tune == u68010) +#define TUNE_68000_10 (TUNE_68000 || TUNE_68010) +#define TUNE_68030 (m68k_tune == u68030 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68040 (m68k_tune == u68040 \ + || m68k_tune == u68020_40 \ + || m68k_tune == u68020_60) +#define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) -#define TUNE_CFV2 TARGET_5200 +#define TUNE_CPU32 (m68k_tune == ucpu32) +#define TUNE_CFV2 (m68k_tune == ucfv2) #define OVERRIDE_OPTIONS override_options() @@ -1104,6 +1148,47 @@ do { if (cc_prev_status.flags & CC_IN_68881) \ #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) -/* Variables in m68k.c */ +/* Values used in the MICROARCH argument to M68K_DEVICE. */ +enum uarch_type +{ + u68000, + u68010, + u68020, + u68020_40, + u68020_60, + u68030, + u68040, + u68060, + ucpu32, + ucfv2, + ucfv3, + ucfv4, + ucfv4e, + ucfv5, + unk_arch +}; + +/* An enumeration of all supported target devices. */ +enum target_device +{ +#define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ + ENUM_VALUE, +#include "m68k-devices.def" +#undef M68K_DEVICE + unk_device +}; + +enum fpu_type +{ + FPUTYPE_NONE, + FPUTYPE_68881, + FPUTYPE_COLDFIRE +}; + +/* Variables in m68k.c; see there for details. */ extern const char *m68k_library_id_string; extern int m68k_last_compare_had_fp_operands; +extern enum target_device m68k_cpu; +extern enum uarch_type m68k_tune; +extern enum fpu_type m68k_fpu; +extern unsigned int m68k_cpu_flags; diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 1379172..af7bd0f 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -20,27 +20,27 @@ ; 02110-1301, USA. m5200 -Target RejectNegative Mask(5200) +Target RejectNegative Generate code for a 520X m5206e -Target RejectNegative Mask(CF_HWDIV) +Target RejectNegative Generate code for a 5206e m528x -Target RejectNegative Mask(528x) +Target RejectNegative Generate code for a 528x m5307 -Target RejectNegative Mask(CFV3) +Target RejectNegative Generate code for a 5307 m5407 -Target RejectNegative Mask(CFV4) +Target RejectNegative Generate code for a 5407 mcfv4e -Target RejectNegative Mask(CFV4E) +Target RejectNegative Generate code for a ColdFire v4e m68000 @@ -48,27 +48,27 @@ Target RejectNegative Generate code for a 68000 m68010 -Target RejectNegative Mask(68010) +Target RejectNegative Generate code for a 68010 m68020 -Target RejectNegative Mask(68020) +Target RejectNegative Generate code for a 68020 m68020-40 -Target RejectNegative Mask(68040) +Target RejectNegative Generate code for a 68040, without any new instructions m68020-60 -Target RejectNegative Mask(68060) +Target RejectNegative Generate code for a 68060, without any new instructions m68030 -Target RejectNegative Mask(68030) +Target RejectNegative Generate code for a 68030 m68040 -Target RejectNegative Mask(68040_ONLY) +Target RejectNegative Generate code for a 68040 m68060 @@ -89,13 +89,17 @@ Target Generate code for a 68851 m68881 -Target RejectNegative Mask(68881) +Target RejectNegative Mask(HARD_FLOAT) Generate code that uses 68881 floating-point instructions malign-int Target Report Mask(ALIGN_INT) Align variables on a 32-bit boundary +march= +Target RejectNegative Joined +Specify the name of the target architecture + mbitfield Target Report RejectNegative Mask(BITFIELD) Use the bit-field instructions @@ -108,10 +112,22 @@ mc68020 Target RejectNegative Generate code for a 68020 +mcpu= +Target RejectNegative Joined +Specify the target CPU + mcpu32 Target RejectNegative Generate code for a cpu32 +mdiv +Target Report Mask(CF_HWDIV) +Use hardware division instructions on ColdFire + +mhard-float +Target RejectNegative Mask(HARD_FLOAT) MaskExists +Generate code which uses hardware floating point instructions + mid-shared-library Target Report Mask(ID_SHARED_LIBRARY) Enable ID based shared library @@ -149,9 +165,13 @@ Target Report RejectNegative Mask(SHORT) Consider type 'int' to be 16 bits wide msoft-float -Target RejectNegative InverseMask(68881) +Target RejectNegative InverseMask(HARD_FLOAT) Generate code with library calls for floating point mstrict-align Target Report Mask(STRICT_ALIGNMENT) Do not use unaligned memory references + +mtune= +Target RejectNegative Joined +Tune for the specified target CPU or architecture diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 427f638..c3dd602 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -3391,9 +3391,9 @@ applications. There are no standard Unix configurations. @end html @heading @anchor{m68k-*-*}m68k-*-* You can specify a default target using @option{--with-cpu=@var{target}}. -The recognized values for @var{target} are: @samp{m68000}, @samp{m68010}, -@samp{m68020}, @samp{m68030}, @samp{m68040}, @samp{m68060}, @samp{m68020-40} -and @samp{m68020-60}. +This @var{target} can either be a @option{-mcpu} argument or one of the +following values: @samp{m68000}, @samp{m68010}, @samp{m68020}, @samp{m68030}, +@samp{m68040}, @samp{m68060}, @samp{m68020-40} and @samp{m68020-60}. @heading @anchor{m68k-hp-hpux}m68k-hp-hpux HP 9000 series 300 or 400 running HP-UX@. HP-UX version 8.0 has a bug in diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ab61a9a..145c322 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -580,10 +580,12 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}} @emph{M680x0 Options} -@gccoptlist{-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol --m68060 -mcpu32 -m5200 -mcfv4e -m68881 -mbitfield @gol --mc68000 -mc68020 @gol --mnobitfield -mrtd -mshort -msoft-float -mpcrel @gol +@gccoptlist{-march=@var{arch} -mcpu=@var{cpu} -mtune=@var{tune} +-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol +-m68060 -mcpu32 -m5200 -m5206e -m528x -m5307 -m5407 @gol +-mcfv4e -mbitfield -mc68000 -mc68020 @gol +-mnobitfield -mrtd -mdiv -mno-div -mshort @gol +-mhard-float -m68881 -msoft-float -mpcrel @gol -malign-int -mstrict-align -msep-data -mno-sep-data @gol -mshared-library-id=n -mid-shared-library -mno-id-shared-library} @@ -10266,18 +10268,88 @@ Indicates that there is no OS function for flushing the cache. @subsection M680x0 Options @cindex M680x0 options -These are the @samp{-m} options defined for the 68000 series. The default -values for these options depends on which style of 68000 was selected when -the compiler was configured; the defaults for the most common choices are -given below. +These are the @samp{-m} options defined for M680x0 and ColdFire processors. +The default settings depend on which architecture was selected when +the compiler was configured; the defaults for the most common choices +are given below. @table @gcctabopt +@item -march=@var{arch} +@opindex march +Generate code for a specific M680x0 or ColdFire instruction set +architecture. Permissible values of @var{arch} for M680x0 +architectures are: @samp{68000}, @samp{68010}, @samp{68020}, +@samp{68030}, @samp{68040}, @samp{68060} and @samp{cpu32}. ColdFire +architectures are selected according to Freescale's ISA classification +and the permissible values are: @samp{isaa}, @samp{isaaplus}, +@samp{isab} and @samp{isac}. + +gcc defines a macro @samp{__mcf@var{arch}__} whenever it is generating +code for a ColdFire target. The @var{arch} in this macro is one of the +@option{-march} arguments given above. + +When used together, @option{-march} and @option{-mtune} select code +that runs on a family of similar processors but that is optimized +for a particular microarchitecture. + +@item -mcpu=@var{cpu} +@opindex mcpu +Generate code for a specific M680x0 or ColdFire processor. +The M680x0 @var{cpu}s are: @samp{68000}, @samp{68010}, @samp{68020}, +@samp{68030}, @samp{68040}, @samp{68060}, @samp{68302}, @samp{68332} +and @samp{cpu32}. The ColdFire @var{cpu}s are given by the table +below, which also classifies the CPUs into families: + +@multitable @columnfractions 0.20 0.80 +@headitem Family @tab @samp{-mcpu} arguments +@item @samp{5206} @tab @samp{5202} @samp{5204} @samp{5206} +@item @samp{5206e} @tab @samp{5206e} +@item @samp{5208} @tab @samp{5207} @samp{5208} +@item @samp{5211a} @tab @samp{5210a} @samp{5211a} +@item @samp{5213} @tab @samp{5211} @samp{5212} @samp{5213} +@item @samp{5216} @tab @samp{5214} @samp{5216} +@item @samp{52235} @tab @samp{52230} @samp{52231} @samp{52232} @samp{52233} @samp{52234} @samp{52235} +@item @samp{5225} @tab @samp{5224} @samp{5225} +@item @samp{5235} @tab @samp{5232} @samp{5233} @samp{5234} @samp{5235} @samp{523x} +@item @samp{5249} @tab @samp{5249} +@item @samp{5250} @tab @samp{5250} +@item @samp{5271} @tab @samp{5270} @samp{5271} +@item @samp{5272} @tab @samp{5272} +@item @samp{5275} @tab @samp{5274} @samp{5275} +@item @samp{5282} @tab @samp{5280} @samp{5281} @samp{5282} @samp{528x} +@item @samp{5307} @tab @samp{5307} +@item @samp{5329} @tab @samp{5327} @samp{5328} @samp{5329} @samp{532x} +@item @samp{5373} @tab @samp{5372} @samp{5373} @samp{537x} +@item @samp{5407} @tab @samp{5407} +@item @samp{5475} @tab @samp{5470} @samp{5471} @samp{5472} @samp{5473} @samp{5474} @samp{5475} @samp{547x} @samp{5480} @samp{5481} @samp{5482} @samp{5483} @samp{5484} @samp{5485} +@end multitable + +@option{-mcpu=@var{cpu}} overrides @option{-march=@var{arch}} if +@var{arch} is compatible with @var{cpu}. Other combinations of +@option{-mcpu} and @option{-march} are rejected. + +@item -mtune=@var{tune} +@opindex mtune +Tune the code for a particular microarchitecture, within the +constraints set by @option{-march} and @option{-mcpu}. +The M680x0 microarchitectures are: @samp{68000}, @samp{68010}, +@samp{68020}, @samp{68030}, @samp{68040}, @samp{68060} +and @samp{cpu32}. The ColdFire microarchitectures +are: @samp{cfv2}, @samp{cfv3}, @samp{cfv4} and @samp{cfv4e}. + +You can also use @option{-mtune=68020-40} for code that needs +to run relatively well on 68020, 68030 and 68040 targets. +@option{-mtune=68020-60} is similar but includes 68060 targets +as well. These two options select the same tuning decisions as +@option{-m68020-40} and @option{-m68020-60} respectively. + @item -m68000 @itemx -mc68000 @opindex m68000 @opindex mc68000 Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. +It is equivalent to @option{-march=68000}. Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. @@ -10286,6 +10358,7 @@ including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. @opindex m68010 Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. +It is equivalent to @option{-march=68010}. @item -m68020 @itemx -mc68020 @@ -10293,22 +10366,19 @@ when the compiler is configured for 68010-based systems. @opindex mc68020 Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. - -@item -m68881 -@opindex m68881 -Generate output containing 68881 instructions for floating point. -This is the default for most 68020 systems unless @option{--nfp} was -specified when the compiler was configured. +It is equivalent to @option{-march=68020}. @item -m68030 @opindex m68030 Generate output for a 68030. This is the default when the compiler is -configured for 68030-based systems. +configured for 68030-based systems. It is equivalent to +@option{-march=68030}. @item -m68040 @opindex m68040 Generate output for a 68040. This is the default when the compiler is -configured for 68040-based systems. +configured for 68040-based systems. It is equivalent to +@option{-march=68040}. This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. Use this option if your 68040 does not @@ -10317,7 +10387,8 @@ have code to emulate those instructions. @item -m68060 @opindex m68060 Generate output for a 68060. This is the default when the compiler is -configured for 68060-based systems. +configured for 68060-based systems. It is equivalent to +@option{-march=68060}. This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on the 68060. Use this option if your 68060 @@ -10327,6 +10398,7 @@ does not have code to emulate those instructions. @opindex mcpu32 Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. +It is equivalent to @option{-march=cpu32}. Use this option for microcontrollers with a CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, @@ -10334,16 +10406,41 @@ CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, @item -m5200 @opindex m5200 -Generate output for a 520X ``coldfire'' family cpu. This is the default +Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 520X-based systems. +It is equivalent to @option{-mcpu=5206}, and is now deprecated +in favor of that option. Use this option for microcontroller with a 5200 core, including -the MCF5202, MCF5203, MCF5204 and MCF5202. +the MCF5202, MCF5203, MCF5204 and MCF5206. + +@item -m5206e +@opindex m5206e +Generate output for a 5206e ColdFire CPU. The option is now +deprecated in favor of the equivalent @option{-mcpu=5206e}. + +@item -m528x +@opindex m528x +Generate output for a member of the ColdFire 528X family. +The option is now deprecated in favor of the equivalent +@option{-mcpu=528x}. + +@item -m5307 +@opindex m5307 +Generate output for a ColdFire 5307 CPU. The option is now deprecated +in favor of the equivalent @option{-mcpu=5307}. + +@item -m5407 +@opindex m5407 +Generate output for a ColdFire 5407 CPU. The option is now deprecated +in favor of the equivalent @option{-mcpu=5407}. @item -mcfv4e @opindex mcfv4e -Generate output for a ColdFire V4e family cpu (e.g.@: 547x/548x). +Generate output for a ColdFire V4e family CPU (e.g.@: 547x/548x). This includes use of hardware floating point instructions. +The option is equivalent to @option{-mcpu=547x}, and is now +deprecated in favor of that option. @item -m68020-40 @opindex m68020-40 @@ -10352,6 +10449,8 @@ This results in code which can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68040. +The option is equivalent to @option{-march=68020} @option{-mtune=68020-40}. + @item -m68020-60 @opindex m68020-60 Generate output for a 68060, without using any of the new instructions. @@ -10359,15 +10458,34 @@ This results in code which can run relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 68881 instructions that are emulated on the 68060. +The option is equivalent to @option{-march=68020} @option{-mtune=68020-60}. + +@item -mhard-float +@itemx -m68881 +@opindex mhard-float +@opindex m68881 +Generate floating-point instructions. This is the default for 68020 +and above, and for ColdFire devices that have an FPU. + @item -msoft-float @opindex msoft-float -Generate output containing library calls for floating point. -@strong{Warning:} the requisite libraries are not available for all m68k -targets. Normally the facilities of the machine's usual C compiler are -used, but this can't be done directly in cross-compilation. You must -make your own arrangements to provide suitable library functions for -cross-compilation. The embedded targets @samp{m68k-*-aout} and -@samp{m68k-*-coff} do provide software floating point support. +Do not generate floating-point instructions; use library calls instead. +This is the default for 68000, 68010, and 68832 targets. It is also +the default for ColdFire devices that have no FPU. + +@item -mdiv +@itemx -mno-div +@opindex mdiv +@opindex mno-div +Generate (do not generate) ColdFire hardware divide and remainder +instructions. If @option{-march} is used without @option{-mcpu}, +the default is ``on'' for ColdFire architectures and ``off'' for M680x0 +architectures. Otherwise, the default is taken from the target CPU +(either the default CPU, or the one specified by @option{-mcpu}). For +example, the default is ``off'' for @option{-mcpu=5206} and ``on'' for +@option{-mcpu=5206e}. + +gcc defines the macro @samp{__mcfhwdiv__} when this option is enabled. @item -mshort @opindex mshort -- 2.7.4