From 8a924bea78f706d517b0b20b458b12a6eccfce1d Mon Sep 17 00:00:00 2001 From: Igor Breger Date: Thu, 23 Mar 2017 12:13:29 +0000 Subject: [PATCH] [GlobalISel][X86] clang-format. NFC llvm-svn: 298590 --- llvm/lib/Target/X86/X86CallLowering.cpp | 17 ++++++++--------- llvm/lib/Target/X86/X86InstructionSelector.cpp | 14 +++++++------- llvm/lib/Target/X86/X86LegalizerInfo.cpp | 1 - llvm/lib/Target/X86/X86RegisterBankInfo.cpp | 5 ++--- llvm/lib/Target/X86/X86RegisterBankInfo.h | 2 +- 5 files changed, 18 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/X86/X86CallLowering.cpp b/llvm/lib/Target/X86/X86CallLowering.cpp index ce905c9..5f8d7f4 100644 --- a/llvm/lib/Target/X86/X86CallLowering.cpp +++ b/llvm/lib/Target/X86/X86CallLowering.cpp @@ -14,14 +14,14 @@ //===----------------------------------------------------------------------===// #include "X86CallLowering.h" +#include "X86CallingConv.h" #include "X86ISelLowering.h" #include "X86InstrInfo.h" #include "X86TargetMachine.h" -#include "X86CallingConv.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/Target/TargetSubtargetInfo.h" using namespace llvm; @@ -116,7 +116,7 @@ bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, }); FuncReturnHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); - if(!handleAssignments(MIRBuilder, SplitArgs, Handler)) + if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) return false; } @@ -137,9 +137,8 @@ struct FormalArgHandler : public CallLowering::ValueHandler { int FI = MFI.CreateFixedObject(Size, Offset, true); MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); - unsigned AddrReg = - MRI.createGenericVirtualRegister(LLT::pointer(0, - DL.getPointerSizeInBits(0))); + unsigned AddrReg = MRI.createGenericVirtualRegister( + LLT::pointer(0, DL.getPointerSizeInBits(0))); MIRBuilder.buildFrameIndex(AddrReg, FI); return AddrReg; } @@ -161,7 +160,7 @@ struct FormalArgHandler : public CallLowering::ValueHandler { const DataLayout &DL; }; -} +} // namespace bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, @@ -169,7 +168,7 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, if (F.arg_empty()) return true; - //TODO: handle variadic function + // TODO: handle variadic function if (F.isVarArg()) return false; @@ -203,7 +202,7 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, MachineBasicBlock &MBB = MIRBuilder.getMBB(); if (!MBB.empty()) - MIRBuilder.setInstr(*MBB.begin()); + MIRBuilder.setInstr(*MBB.begin()); FormalArgHandler Handler(MIRBuilder, MRI, CC_X86, DL); if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index 2dbe4b4..f572538 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -118,13 +118,13 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, // No need to constrain SrcReg. It will get constrained when // we hit another of its use or its defs. // Copies do not have constraints. - const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); + const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); if (!OldRC || !RC->hasSubClassEq(OldRC)) { if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) { - DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) - << " operand\n"); - return false; - } + DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) + << " operand\n"); + return false; + } } I.setDesc(TII.get(X86::COPY)); return true; @@ -152,7 +152,8 @@ bool X86InstructionSelector::select(MachineInstr &I) const { assert(I.getNumOperands() == I.getNumExplicitOperands() && "Generic instruction has unexpected implicit operands\n"); - // TODO: This should be implemented by tblgen, pattern with predicate not supported yet. + // TODO: This should be implemented by tblgen, pattern with predicate not + // supported yet. if (selectBinaryOp(I, MRI)) return true; @@ -300,4 +301,3 @@ bool X86InstructionSelector::selectBinaryOp(MachineInstr &I, return constrainSelectedInstRegOperands(I, TII, TRI, RBI); } - diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index 06c11c8..4e94e45 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -85,5 +85,4 @@ void X86LegalizerInfo::setLegalizerInfoSSE2() { for (unsigned BinOp : {G_ADD, G_SUB}) for (auto Ty : {v4s32}) setAction({BinOp, Ty}, Legal); - } diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp index fd9f624..c06e4ba 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp @@ -72,8 +72,7 @@ X86RegisterBankInfo::getOperandsMapping(const MachineInstr &MI, bool isFP) { unsigned NumOperands = MI.getNumOperands(); LLT Ty = MRI.getType(MI.getOperand(0).getReg()); - if (NumOperands != 3 || - (Ty != MRI.getType(MI.getOperand(1).getReg())) || + if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) || (Ty != MRI.getType(MI.getOperand(2).getReg()))) llvm_unreachable("Unsupported operand maping yet."); @@ -106,7 +105,7 @@ X86RegisterBankInfo::getOperandsMapping(const MachineInstr &MI, bool isFP) { ValMapIdx = VMI_3OpsFp64Idx; break; default: - llvm_unreachable("Unsupported register size."); + llvm_unreachable("Unsupported register size."); } } } else { diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.h b/llvm/lib/Target/X86/X86RegisterBankInfo.h index 74af266..a463551 100644 --- a/llvm/lib/Target/X86/X86RegisterBankInfo.h +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.h @@ -50,5 +50,5 @@ public: InstructionMapping getInstrMapping(const MachineInstr &MI) const override; }; -} // End llvm namespace. +} // namespace llvm #endif -- 2.7.4