From 8a84fc6bf7cd9de567a13ced6cd4f481274f006d Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 25 Aug 2011 16:41:19 +1000 Subject: [PATCH] microblaze: Add an MSR_PVR constant and use it. Signed-off-by: Edgar E. Iglesias --- target-microblaze/cpu.h | 1 + target-microblaze/translate.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index a81da62..3530286 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -65,6 +65,7 @@ struct CPUMBState; #define MSR_DCE (1<<7) /* 0x080 */ #define MSR_EE (1<<8) /* 0x100 */ #define MSR_EIP (1<<9) /* 0x200 */ +#define MSR_PVR (1<<10) /* 0x400 */ #define MSR_CC (1<<31) /* Machine State Register (MSR) Fields */ diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 15f1fe5..366fd3e 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -429,8 +429,8 @@ static inline void msr_write(DisasContext *dc, TCGv v) t = tcg_temp_new(); dc->cpustate_changed = 1; /* PVR bit is not writable. */ - tcg_gen_andi_tl(t, v, ~(1 << 10)); - tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10)); + tcg_gen_andi_tl(t, v, ~MSR_PVR); + tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); tcg_temp_free(t); } -- 2.7.4