From 8a2a73056fae5cae440faae840fd04afa5328fdf Mon Sep 17 00:00:00 2001 From: denisc Date: Wed, 3 May 2000 19:20:09 +0000 Subject: [PATCH] * config/avr/avr-protos.h (test_hard_reg_class): Declared. * config/avr/avr.c (ashrhi3_out): optimized shift by 15. (lshrhi3_out): Likewise. (ashrsi3_out): bugfix in shift by 8. (test_hard_reg_class): New function. * config/avr/avr.md: Bugfix inside conditions in peepholes. (ashlhi3): removed define_expand of this pattern. (*ashlhi3_insn): renamed to ashlhi3. (ashlsi3): removed define_expand of this pattern. (*ashlsi3_insn): renamed to ashlsi3. (ashrqi3): removed define_expand of this pattern. (*ashrqi3_insn): renamed to ashrqi3. (ashrhi3): removed define_expand of this pattern. (*ashrhi3_insn): renamed to ashrhi3. (ashrsi3): removed define_expand of this pattern. (*ashrsi3_insn): renamed to ashrsi3. (lshrhi3): removed define_expand of this pattern. (*lshrhi3_insn): renamed to lshrhi3. (lshrsi3): removed define_expand of this pattern. (*lshrsi3_insn): renamed to lshrsi3. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@33640 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 23 +++++++++++++ gcc/config/avr/avr-protos.h | 3 +- gcc/config/avr/avr.c | 24 +++++++++++-- gcc/config/avr/avr.md | 83 +++++++-------------------------------------- 4 files changed, 59 insertions(+), 74 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0e11f94..ec59f5f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +Wed May 3 22:52:53 2000 Denis Chertykov + + * config/avr/avr-protos.h (test_hard_reg_class): Declared. + * config/avr/avr.c (ashrhi3_out): optimized shift by 15. + (lshrhi3_out): Likewise. + (ashrsi3_out): bugfix in shift by 8. + (test_hard_reg_class): New function. + * config/avr/avr.md: Bugfix inside conditions in peepholes. + (ashlhi3): removed define_expand of this pattern. + (*ashlhi3_insn): renamed to ashlhi3. + (ashlsi3): removed define_expand of this pattern. + (*ashlsi3_insn): renamed to ashlsi3. + (ashrqi3): removed define_expand of this pattern. + (*ashrqi3_insn): renamed to ashrqi3. + (ashrhi3): removed define_expand of this pattern. + (*ashrhi3_insn): renamed to ashrhi3. + (ashrsi3): removed define_expand of this pattern. + (*ashrsi3_insn): renamed to ashrsi3. + (lshrhi3): removed define_expand of this pattern. + (*lshrhi3_insn): renamed to lshrhi3. + (lshrsi3): removed define_expand of this pattern. + (*lshrsi3_insn): renamed to lshrsi3. + 2000-05-03 Rodney Brown * config/mcore/mcore.c: Replacing inclusion of "stdio,h" with diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index fc525c2..605c2a3 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -107,9 +107,9 @@ extern char * lshrqi3_out PARAMS ((rtx insn, rtx operands[], int *len)); extern char * lshrhi3_out PARAMS ((rtx insn, rtx operands[], int *len)); extern char * lshrsi3_out PARAMS ((rtx insn, rtx operands[], int *len)); -extern int avr_address_cost PARAMS ((rtx x)); extern enum reg_class preferred_reload_class PARAMS ((rtx x, enum reg_class class)); +extern int avr_address_cost PARAMS ((rtx x)); extern int extra_constraint PARAMS ((rtx x, char c)); extern rtx legitimize_address PARAMS ((rtx x, rtx oldx, enum machine_mode mode)); @@ -135,6 +135,7 @@ extern int _reg_unused_after PARAMS ((rtx insn, rtx reg)); extern int avr_jump_mode PARAMS ((rtx x, rtx insn)); extern int byte_immediate_operand PARAMS ((register rtx op, enum machine_mode mode)); +extern int test_hard_reg_class PARAMS ((enum reg_class class, rtx x)); #endif /* RTX_CODE */ diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index df05ca6..c2fe4ed 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -2401,6 +2401,10 @@ ashrhi3_out (insn,operands,len) return *len = 3, (AS1 (clr,%B0) CR_TAB AS2 (sbrc,%A0,7) CR_TAB AS1 (dec,%B0)); + case 15: + return *len = 3, (AS1 (lsl,%B0) CR_TAB + AS2 (sbc,%A0,%A0) CR_TAB + AS2 (mov,%B0,%A0)); } } if (len) @@ -2455,7 +2459,7 @@ ashrsi3_out (insn,operands,len) AS1 (dec,%D0)); else return (AS1 (clr,%D0) CR_TAB - AS2 (sbrc,%C0,7) CR_TAB + AS2 (sbrc,%D1,7) CR_TAB AS1 (dec,%D0) CR_TAB AS2 (mov,%C0,%D1) CR_TAB AS2 (mov,%B0,%C1) CR_TAB @@ -2634,7 +2638,12 @@ lshrhi3_out (insn,operands,len) AS1 (clr,%B0)); else return *len = 1, AS1 (clr,%B0); - + + case 15: + return *len = 4, (AS1 (lsl,%B0) CR_TAB + AS2 (sbc,%A0,%A0) CR_TAB + AS1 (neg,%A0) CR_TAB + AS1 (clr,%B0)); } } if (len) @@ -3736,6 +3745,17 @@ preferred_reload_class(x,class) return class; } +int +test_hard_reg_class(class, x) + enum reg_class class; + rtx x; +{ + int regno = true_regnum (x); + if (regno < 0) + return 0; + return TEST_HARD_REG_CLASS (class, regno); +} + void debug_hard_reg_set (HARD_REG_SET set) { diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index f90db47..019c36b 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -877,15 +877,7 @@ [(set_attr "length" "6,4,6,7") (set_attr "cc" "clobber,set_czn,set_czn,clobber")]) -(define_expand "ashlhi3" - [(parallel [(set (match_operand:HI 0 "register_operand" "") - (ashift:HI (match_operand:HI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*ashlhi3_insn" +(define_insn "ashlhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0") (match_operand:QI 2 "general_operand" "r,P,O,K,i,Qm"))) @@ -895,15 +887,7 @@ [(set_attr "length" "7,2,4,2,5,8") (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")]) -(define_expand "ashlsi3" - [(parallel [(set (match_operand:SI 0 "register_operand" "") - (ashift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*ashlsi3_insn" +(define_insn "ashlsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0") (match_operand:QI 2 "general_operand" "r,P,O,i,Qm"))) @@ -916,15 +900,7 @@ ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> ;; arithmetic shift right -(define_expand "ashrqi3" - [(parallel [(set (match_operand:QI 0 "register_operand" "") - (ashiftrt:QI (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*ashrqi3" +(define_insn "ashrqi3" [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0") (match_operand:QI 2 "general_operand" "r,P,K,i,Qm"))) @@ -934,16 +910,7 @@ [(set_attr "length" "6,1,2,4,7") (set_attr "cc" "clobber,clobber,clobber,clobber,clobber")]) - -(define_expand "ashrhi3" - [(parallel [(set (match_operand:HI 0 "register_operand" "") - (ashiftrt:HI (match_operand:HI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*ashrhi3_insn" +(define_insn "ashrhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0") (match_operand:QI 2 "general_operand" "r,P,K,O,i,Qm"))) @@ -953,15 +920,7 @@ [(set_attr "length" "7,2,4,2,5,8") (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")]) -(define_expand "ashrsi3" - [(parallel [(set (match_operand:SI 0 "register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*ashrsi3_insn" +(define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0") (match_operand:QI 2 "general_operand" "r,P,O,i,Qm"))) @@ -983,15 +942,7 @@ [(set_attr "length" "6,4,6,7") (set_attr "cc" "clobber,set_czn,set_czn,clobber")]) -(define_expand "lshrhi3" - [(parallel [(set (match_operand:HI 0 "register_operand" "") - (lshiftrt:HI (match_operand:HI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*lshrhi3_insn" +(define_insn "lshrhi3" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0") (match_operand:QI 2 "general_operand" "r,P,K,O,i,Qm"))) @@ -1001,17 +952,7 @@ [(set_attr "length" "7,2,4,2,5,8") (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")]) - - -(define_expand "lshrsi3" - [(parallel [(set (match_operand:SI 0 "register_operand" "") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "") - (match_operand:QI 2 "general_operand" ""))) - (clobber (match_scratch:QI 3 ""))])] - "" - "") - -(define_insn "*lshrsi3_insn" +(define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0") (match_operand:QI 2 "general_operand" "r,P,O,i,Qm"))) @@ -1815,8 +1756,8 @@ (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 2 "" "")) (pc)))] - "(true_regnum (operands[0]) >= LD_REGS - && true_regnum (operands[1]) >= LD_REGS)" + "(test_hard_reg_class (LD_REGS, operands[0]) + && test_hard_reg_class (LD_REGS, operands[1]))" "* { if (TEST_HARD_REG_CLASS (ADDW_REGS, true_regnum (operands[0]))) @@ -1853,8 +1794,8 @@ (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 2 "" "")) (pc)))] - "(true_regnum (operands[0]) >= LD_REGS - && true_regnum (operands[1]) >= LD_REGS)" + "(test_hard_reg_class (LD_REGS, operands[0]) + && test_hard_reg_class (LD_REGS, operands[1]))" "* { if (TEST_HARD_REG_CLASS (ADDW_REGS, true_regnum (operands[0]))) @@ -1885,7 +1826,7 @@ (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 1 "" "")) (pc)))] - "(true_regnum (operands[0]) >= LD_REGS)" + "test_hard_reg_class (LD_REGS, operands[0])" "* { output_asm_insn (AS2 (subi,%A0,1), operands); -- 2.7.4