From 89f8a707d00890d302f6d4320d4ecdba12c26bdf Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 7 Jun 2021 15:05:46 -0400 Subject: [PATCH] dt-bindings: clk: vc5: Fix example The example properties do not match the binding. Fix them, and prohibit undocumented properties in clock nodes to prevent this from happening in the future. Fixes: 45c940184b50 ("dt-bindings: clk: versaclock5: convert to yaml") Signed-off-by: Sean Anderson Reviewed-by: Luca Ceresoli Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/clock/idt,versaclock5.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml index c268deb..241e1f2 100644 --- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml @@ -86,6 +86,7 @@ patternProperties: description: The Slew rate control for CMOS single-ended. $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 80, 85, 90, 100 ] + additionalProperties: false required: - compatible @@ -141,13 +142,13 @@ examples: clock-names = "xin"; OUT1 { - idt,drive-mode = ; - idt,voltage-microvolts = <1800000>; + idt,mode = ; + idt,voltage-microvolt = <1800000>; idt,slew-percent = <80>; }; OUT4 { - idt,drive-mode = ; + idt,mode = ; }; }; }; -- 2.7.4