From 89f7ccea6f6488c443655880229c54db1f180153 Mon Sep 17 00:00:00 2001
From: vnalamot <VenkataRamanaiah.Nalamothu@amd.com>
Date: Tue, 20 Oct 2020 22:01:09 +0530
Subject: [PATCH] [AMDGPU] Remove getAllVGPR32() which cannot handle Accum
 VGPRs properly

Remove getAllVGPR32() interface and update the SGPR spill code to use
a proper method to get the relevant VGPR registers list.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D89806
---
 llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 17 ++++++-----------
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp    |  5 -----
 llvm/lib/Target/AMDGPU/SIRegisterInfo.h      |  4 ----
 3 files changed, 6 insertions(+), 20 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 9d1ecae..17f8257 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -242,19 +242,14 @@ static bool lowerShiftReservedVGPR(MachineFunction &MF,
 
   // If there are no free lower VGPRs available, default to using the
   // pre-reserved register instead.
-  Register LowestAvailableVGPR = PreReservedVGPR;
-
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
-  ArrayRef<MCPhysReg> AllVGPR32s = ST.getRegisterInfo()->getAllVGPR32(MF);
-  for (MCPhysReg Reg : AllVGPR32s) {
-    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg)) {
-      LowestAvailableVGPR = Reg;
-      break;
-    }
-  }
+  const SIRegisterInfo *TRI = ST.getRegisterInfo();
+  Register LowestAvailableVGPR =
+      TRI->findUnusedRegister(MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF);
+  if (!LowestAvailableVGPR)
+    LowestAvailableVGPR = PreReservedVGPR;
 
   const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
+  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
   Optional<int> FI;
   // Check if we are reserving a CSR. Create a stack object for a possible spill
   // in the function prologue.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 9782e11..c7a0121 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1989,8 +1989,3 @@ ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
 }
-
-ArrayRef<MCPhysReg>
-SIRegisterInfo::getAllVGPR32(const MachineFunction &MF) const {
-  return makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), ST.getMaxNumVGPRs(MF));
-}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 5b50026..6cae479 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -326,10 +326,6 @@ public:
   /// of the subtarget.
   ArrayRef<MCPhysReg> getAllSGPR32(const MachineFunction &MF) const;
 
-  /// Return all VGPR32 which satisfy the waves per execution unit requirement
-  /// of the subtarget.
-  ArrayRef<MCPhysReg> getAllVGPR32(const MachineFunction &MF) const;
-
 private:
   void buildSpillLoadStore(MachineBasicBlock::iterator MI,
                            unsigned LoadStoreOp,
-- 
2.7.4