From 89c69c260e607c6437029c5d1356096d9e3b2b9a Mon Sep 17 00:00:00 2001
From: "yanhong.wang" <yanhong.wang@starfivetech.com>
Date: Wed, 8 Jun 2022 11:27:27 +0800
Subject: [PATCH] dt-bindings:uart:jh7110: Add uart3-uart5 support

Add bindings for uart3-uart5 on the StarFive JH7100 SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi  |   6 +-
 arch/riscv/boot/dts/starfive/jh7110.dtsi         |  18 ++-
 arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi | 136 +++++++++++++++++++++++
 3 files changed, 151 insertions(+), 9 deletions(-)
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110-common.dtsi
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
 mode change 100755 => 100644 arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
old mode 100755
new mode 100644
index 1cafa59c..94f2689
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -413,17 +413,17 @@
 &can0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&can0_pins>;
-	status = "okay";
+	status = "disabled";
 };
 
 &can1 {
-	status = "okay";
+	status = "disabled";
 };
 
 &tdm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&tdm0_pins>;
-	status = "okay";
+	status = "disabled";
 };
 
 &spdif0 {
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
old mode 100755
new mode 100644
index cc4165e..c38fbf9
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -417,7 +417,8 @@
 			clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 				 <&clkgen JH7110_UART0_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U0_DW_UART_APB>;
+			resets = <&rstgen RSTN_U0_DW_UART_APB>,
+				<&rstgen RSTN_U0_DW_UART_CORE>;
 			interrupts = <32>;
 			status = "disabled";
 		};
@@ -430,7 +431,8 @@
 			clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 				 <&clkgen JH7110_UART1_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U1_DW_UART_APB>;
+			resets = <&rstgen RSTN_U1_DW_UART_APB>,
+				<&rstgen RSTN_U1_DW_UART_CORE>;
 			interrupts = <33>;
 			status = "disabled";
 		};
@@ -443,7 +445,8 @@
 			clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 				 <&clkgen JH7110_UART2_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U2_DW_UART_APB>;
+			resets = <&rstgen RSTN_U2_DW_UART_APB>,
+				<&rstgen RSTN_U2_DW_UART_CORE>;
 			interrupts = <34>;
 			status = "disabled";
 		};
@@ -456,7 +459,8 @@
 			clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 				 <&clkgen JH7110_UART3_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U3_DW_UART_APB>;
+			resets = <&rstgen RSTN_U3_DW_UART_APB>,
+				<&rstgen RSTN_U3_DW_UART_CORE>;
 			interrupts = <45>;
 			status = "disabled";
 		};
@@ -469,7 +473,8 @@
 			clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 				 <&clkgen JH7110_UART4_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U4_DW_UART_APB>;
+			resets = <&rstgen RSTN_U4_DW_UART_APB>,
+				<&rstgen RSTN_U4_DW_UART_CORE>;
 			interrupts = <46>;
 			status = "disabled";
 		};
@@ -482,7 +487,8 @@
 			clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 				 <&clkgen JH7110_UART5_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U5_DW_UART_APB>;
+			resets = <&rstgen RSTN_U5_DW_UART_APB>,
+				<&rstgen RSTN_U5_DW_UART_CORE>;
 			interrupts = <47>;
 			status = "disabled";
 		};
diff --git a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
old mode 100755
new mode 100644
index 76447af..c67495a
--- a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
@@ -42,6 +42,74 @@
 		};
 	};
 
+	uart1_pins: uart1-pins {
+		uart1-pins-tx {
+			sf,pins = <PAD_GPIO41>;
+			sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+			sf,pin-gpio-dout = <GPO_UART1_SOUT>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+
+		uart1-pins-rx {
+			sf,pins = <PAD_GPIO42>;
+			sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART1_SIN>;
+		};
+
+		uart1-pins-cts {
+			sf,pins = <PAD_GPIO43>;
+			sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART1_CTS_N>;
+		};
+
+		uart1-pins-rts {
+			sf,pins = <PAD_GPIO40>;
+			sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-dout = <GPO_UART1_RTS_N>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		uart2-pins-tx {
+			sf,pins = <PAD_GPIO41>;
+			sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+			sf,pin-gpio-dout = <GPO_UART2_SOUT>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+
+		uart2-pins-rx {
+			sf,pins = <PAD_GPIO42>;
+			sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART2_SIN>;
+		};
+
+		uart2-pins-cts {
+			sf,pins = <PAD_GPIO43>;
+			sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART2_CTS_N>;
+		};
+
+		uart2-pins-rts {
+			sf,pins = <PAD_GPIO40>;
+			sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-dout = <GPO_UART2_RTS_N>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+	};
+
 	uart3_pins: uart3-pins {
 		uart3-pins-tx {
 			sf,pins = <PAD_GPIO30>;
@@ -60,6 +128,74 @@
 		};
 	};
 
+	uart4_pins: uart4-pins {
+		uart4-pins-tx {
+			sf,pins = <PAD_GPIO41>;
+			sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+			sf,pin-gpio-dout = <GPO_UART4_SOUT>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+
+		uart4-pins-rx {
+			sf,pins = <PAD_GPIO42>;
+			sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART4_SIN>;
+		};
+
+		uart4-pins-cts {
+			sf,pins = <PAD_GPIO43>;
+			sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART4_CTS_N>;
+		};
+
+		uart4-pins-rts {
+			sf,pins = <PAD_GPIO40>;
+			sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-dout = <GPO_UART4_RTS_N>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+	};
+
+	uart5_pins: uart5-pins {
+		uart5-pins-tx {
+			sf,pins = <PAD_GPIO41>;
+			sf,pinmux = <PAD_GPIO41_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_DS(3))>;
+			sf,pin-gpio-dout = <GPO_UART5_SOUT>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+
+		uart5-pins-rx {
+			sf,pins = <PAD_GPIO42>;
+			sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1)|GPIO_PU(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART5_SIN>;
+		};
+
+		uart5-pins-cts {
+			sf,pins = <PAD_GPIO43>;
+			sf,pinmux = <PAD_GPIO43_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-doen = <OEN_HIGH>;
+			sf,pin-gpio-din =  <GPI_UART5_CTS_N>;
+		};
+
+		uart5-pins-rts {
+			sf,pins = <PAD_GPIO40>;
+			sf,pinmux = <PAD_GPIO40_FUNC_SEL 0>;
+			sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+			sf,pin-gpio-dout = <GPO_UART5_RTS_N>;
+			sf,pin-gpio-doen = <OEN_LOW>;
+		};
+	};
+
 	i2c0_pins: i2c0-pins {
 		i2c0-pins-scl {
 			sf,pins = <PAD_GPIO36>;
-- 
2.7.4