From 897d4c6fe954709a9325fc29171663962595dc6d Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 13 Jan 2019 21:50:24 +0000 Subject: [PATCH] [DAGCombiner] Some very basic add/sub saturation combines. Handle combines with zero and constant canonicalization for adds. llvm-svn: 351024 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 64 +++++++++++++++++++++++++++ llvm/test/CodeGen/X86/combine-add-ssat.ll | 26 +++-------- llvm/test/CodeGen/X86/combine-add-usat.ll | 18 ++------ llvm/test/CodeGen/X86/combine-sub-ssat.ll | 22 ++------- llvm/test/CodeGen/X86/combine-sub-usat.ll | 18 ++------ 5 files changed, 82 insertions(+), 66 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 12b03f3..104b8d0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -293,6 +293,8 @@ namespace { SDValue visitADD(SDNode *N); SDValue visitADDLike(SDValue N0, SDValue N1, SDNode *LocReference); SDValue visitSUB(SDNode *N); + SDValue visitADDSAT(SDNode *N); + SDValue visitSUBSAT(SDNode *N); SDValue visitADDC(SDNode *N); SDValue visitUADDO(SDNode *N); SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N); @@ -1486,6 +1488,10 @@ SDValue DAGCombiner::visit(SDNode *N) { case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); case ISD::ADD: return visitADD(N); case ISD::SUB: return visitSUB(N); + case ISD::SADDSAT: + case ISD::UADDSAT: return visitADDSAT(N); + case ISD::SSUBSAT: + case ISD::USUBSAT: return visitSUBSAT(N); case ISD::ADDC: return visitADDC(N); case ISD::UADDO: return visitUADDO(N); case ISD::SUBC: return visitSUBC(N); @@ -2170,6 +2176,39 @@ SDValue DAGCombiner::visitADD(SDNode *N) { return SDValue(); } +SDValue DAGCombiner::visitADDSAT(SDNode *N) { + unsigned Opcode = N->getOpcode(); + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + EVT VT = N0.getValueType(); + SDLoc DL(N); + + // fold vector ops + if (VT.isVector()) { + // TODO SimplifyVBinOp + + // fold (add_sat x, 0) -> x, vector edition + if (ISD::isBuildVectorAllZeros(N1.getNode())) + return N0; + if (ISD::isBuildVectorAllZeros(N0.getNode())) + return N1; + } + + if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) { + // canonicalize constant to RHS + if (!DAG.isConstantIntBuildVectorOrConstantInt(N1)) + return DAG.getNode(Opcode, DL, VT, N1, N0); + + // TODO Constant Folding + } + + // fold (add_sat x, 0) -> x + if (isNullConstant(N1)) + return N0; + + return SDValue(); +} + static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) { bool Masked = false; @@ -2732,6 +2771,31 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { return SDValue(); } +SDValue DAGCombiner::visitSUBSAT(SDNode *N) { + unsigned Opcode = N->getOpcode(); + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + EVT VT = N0.getValueType(); + SDLoc DL(N); + + // fold vector ops + if (VT.isVector()) { + // TODO SimplifyVBinOp + + // fold (sub_sat x, 0) -> x, vector edition + if (ISD::isBuildVectorAllZeros(N1.getNode())) + return N0; + } + + // TODO Constant Folding + + // fold (sub_sat x, 0) -> x + if (isNullConstant(N1)) + return N0; + + return SDValue(); +} + SDValue DAGCombiner::visitSUBC(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); diff --git a/llvm/test/CodeGen/X86/combine-add-ssat.ll b/llvm/test/CodeGen/X86/combine-add-ssat.ll index 1da3229..217e91a 100644 --- a/llvm/test/CodeGen/X86/combine-add-ssat.ll +++ b/llvm/test/CodeGen/X86/combine-add-ssat.ll @@ -17,10 +17,10 @@ define i32 @combine_constant_i32(i32 %a0) { ; CHECK: # %bb.0: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movl %edi, %ecx -; CHECK-NEXT: addl $1, %ecx +; CHECK-NEXT: incl %ecx ; CHECK-NEXT: setns %al ; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF -; CHECK-NEXT: addl $1, %edi +; CHECK-NEXT: incl %edi ; CHECK-NEXT: cmovnol %edi, %eax ; CHECK-NEXT: retq %res = call i32 @llvm.sadd.sat.i32(i32 1, i32 %a0); @@ -45,30 +45,16 @@ define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) { define i32 @combine_zero_i32(i32 %a0) { ; CHECK-LABEL: combine_zero_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movl %edi, %ecx -; CHECK-NEXT: addl $0, %ecx -; CHECK-NEXT: setns %al -; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF -; CHECK-NEXT: addl $0, %edi -; CHECK-NEXT: cmovnol %edi, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %1 = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 0); ret i32 %1 } define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) { -; SSE-LABEL: combine_zero_v8i16: -; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: paddsw %xmm1, %xmm0 -; SSE-NEXT: retq -; -; AVX-LABEL: combine_zero_v8i16: -; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpaddsw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq +; CHECK-LABEL: combine_zero_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: retq %1 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer); ret <8 x i16> %1 } diff --git a/llvm/test/CodeGen/X86/combine-add-usat.ll b/llvm/test/CodeGen/X86/combine-add-usat.ll index 531f744..9492320 100644 --- a/llvm/test/CodeGen/X86/combine-add-usat.ll +++ b/llvm/test/CodeGen/X86/combine-add-usat.ll @@ -41,26 +41,16 @@ define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) { define i32 @combine_zero_i32(i32 %a0) { ; CHECK-LABEL: combine_zero_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: addl $0, %edi -; CHECK-NEXT: movl $-1, %eax -; CHECK-NEXT: cmovael %edi, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %1 = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 0); ret i32 %1 } define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) { -; SSE-LABEL: combine_zero_v8i16: -; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: paddusw %xmm1, %xmm0 -; SSE-NEXT: retq -; -; AVX-LABEL: combine_zero_v8i16: -; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq +; CHECK-LABEL: combine_zero_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: retq %1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer); ret <8 x i16> %1 } diff --git a/llvm/test/CodeGen/X86/combine-sub-ssat.ll b/llvm/test/CodeGen/X86/combine-sub-ssat.ll index 8d53300..a17573d 100644 --- a/llvm/test/CodeGen/X86/combine-sub-ssat.ll +++ b/llvm/test/CodeGen/X86/combine-sub-ssat.ll @@ -15,30 +15,16 @@ declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) define i32 @combine_zero_i32(i32 %a0) { ; CHECK-LABEL: combine_zero_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: movl %edi, %ecx -; CHECK-NEXT: subl $0, %ecx -; CHECK-NEXT: setns %al -; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF -; CHECK-NEXT: subl $0, %edi -; CHECK-NEXT: cmovnol %edi, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %1 = call i32 @llvm.ssub.sat.i32(i32 %a0, i32 0); ret i32 %1 } define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) { -; SSE-LABEL: combine_zero_v8i16: -; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: psubsw %xmm1, %xmm0 -; SSE-NEXT: retq -; -; AVX-LABEL: combine_zero_v8i16: -; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpsubsw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq +; CHECK-LABEL: combine_zero_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: retq %1 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer); ret <8 x i16> %1 } diff --git a/llvm/test/CodeGen/X86/combine-sub-usat.ll b/llvm/test/CodeGen/X86/combine-sub-usat.ll index 0568b28..94d8aec 100644 --- a/llvm/test/CodeGen/X86/combine-sub-usat.ll +++ b/llvm/test/CodeGen/X86/combine-sub-usat.ll @@ -15,26 +15,16 @@ declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) define i32 @combine_zero_i32(i32 %a0) { ; CHECK-LABEL: combine_zero_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: subl $0, %edi -; CHECK-NEXT: cmovael %edi, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %1 = call i32 @llvm.usub.sat.i32(i32 %a0, i32 0); ret i32 %1 } define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) { -; SSE-LABEL: combine_zero_v8i16: -; SSE: # %bb.0: -; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: psubusw %xmm1, %xmm0 -; SSE-NEXT: retq -; -; AVX-LABEL: combine_zero_v8i16: -; AVX: # %bb.0: -; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: retq +; CHECK-LABEL: combine_zero_v8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: retq %1 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer); ret <8 x i16> %1 } -- 2.7.4