From 892d9f06d03b255bdc414ee17992b3843943bcbd Mon Sep 17 00:00:00 2001 From: Davide Italiano Date: Sat, 30 Jul 2016 22:07:18 +0000 Subject: [PATCH] [HexagonBitSimplify] Remove dead code. llvm-svn: 277284 --- llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index c847fc1..d8babdd 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1331,7 +1331,6 @@ namespace { bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override; static bool isTfrConst(const MachineInstr &MI); private: - bool isConst(unsigned R, int64_t &V) const; unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C, MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL); @@ -1341,23 +1340,6 @@ namespace { }; } -bool ConstGeneration::isConst(unsigned R, int64_t &C) const { - if (!BT.has(R)) - return false; - const BitTracker::RegisterCell &RC = BT.lookup(R); - int64_t T = 0; - for (unsigned i = RC.width(); i > 0; --i) { - const BitTracker::BitValue &V = RC[i-1]; - T <<= 1; - if (V.is(1)) - T |= 1; - else if (!V.is(0)) - return false; - } - C = T; - return true; -} - bool ConstGeneration::isTfrConst(const MachineInstr &MI) { unsigned Opc = MI.getOpcode(); switch (Opc) { -- 2.7.4