From 8909dc5ebe8ad39f1743131eb70df402d796acab Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 12 Nov 2021 16:26:13 -0800 Subject: [PATCH] [RISCV] Fixed duplicate RUN line on float-intrinsics.ll. NFC We had two identical RV64I RUN lines. One should be RV32I. --- llvm/test/CodeGen/RISCV/float-intrinsics.ll | 270 +++++++++++++++++++++++++++- 1 file changed, 268 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll index e5b2ce6..13cb256 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -7,8 +7,8 @@ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ -; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ +; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s @@ -29,6 +29,15 @@ define float @sqrt_f32(float %a) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: sqrt_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call sqrtf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: sqrt_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -63,6 +72,15 @@ define float @powi_f32(float %a, i32 %b) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: powi_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call __powisf2@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: powi_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -97,6 +115,15 @@ define float @sin_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: sin_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: sin_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -130,6 +157,15 @@ define float @cos_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: cos_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: cos_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -184,6 +220,26 @@ define float @sincos_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 32 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: sincos_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s0, a0 +; RV32I-NEXT: call sinf@plt +; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call cosf@plt +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: sincos_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -32 @@ -230,6 +286,15 @@ define float @pow_f32(float %a, float %b) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: pow_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call powf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: pow_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -263,6 +328,15 @@ define float @exp_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: exp_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call expf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: exp_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -296,6 +370,15 @@ define float @exp2_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: exp2_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call exp2f@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: exp2_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -329,6 +412,15 @@ define float @log_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: log_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call logf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: log_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -362,6 +454,15 @@ define float @log10_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: log10_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call log10f@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: log10_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -395,6 +496,15 @@ define float @log2_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: log2_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call log2f@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: log2_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -428,6 +538,15 @@ define float @fma_f32(float %a, float %b, float %c) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: fma_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call fmaf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: fma_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -461,6 +580,20 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: fmuladd_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: mv s0, a2 +; RV32I-NEXT: call __mulsf3@plt +; RV32I-NEXT: mv a1, s0 +; RV32I-NEXT: call __addsf3@plt +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: fmuladd_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -495,6 +628,13 @@ define float @fabs_f32(float %a) nounwind { ; RV64IF-NEXT: and a0, a0, a1 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: fabs_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a1, 524288 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: and a0, a0, a1 +; RV32I-NEXT: ret +; ; RV64I-LABEL: fabs_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 524288 @@ -524,6 +664,15 @@ define float @minnum_f32(float %a, float %b) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: minnum_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call fminf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: minnum_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -555,6 +704,15 @@ define float @maxnum_f32(float %a, float %b) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: maxnum_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call fmaxf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: maxnum_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -603,6 +761,15 @@ define float @copysign_f32(float %a, float %b) nounwind { ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: copysign_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 524288 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: addi a2, a2, -1 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: ret +; ; RV64I-LABEL: copysign_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a2, 524288 @@ -636,6 +803,15 @@ define float @floor_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: floor_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call floorf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: floor_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -669,6 +845,15 @@ define float @ceil_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: ceil_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call ceilf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: ceil_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -702,6 +887,15 @@ define float @trunc_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: trunc_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call truncf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: trunc_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -735,6 +929,15 @@ define float @rint_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: rint_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call rintf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: rint_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -768,6 +971,15 @@ define float @nearbyint_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: nearbyint_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call nearbyintf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: nearbyint_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -801,6 +1013,15 @@ define float @round_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: round_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call roundf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: round_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -834,6 +1055,15 @@ define float @roundeven_f32(float %a) nounwind { ; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: roundeven_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call roundevenf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: roundeven_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -861,6 +1091,15 @@ define iXLen @lrint_f32(float %a) nounwind { ; RV64IF-NEXT: fcvt.l.s a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: lrint_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call lrintf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: lrint_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -888,6 +1127,15 @@ define iXLen @lround_f32(float %a) nounwind { ; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm ; RV64IF-NEXT: ret ; +; RV32I-LABEL: lround_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call lroundf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: lround_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -918,6 +1166,15 @@ define i64 @llrint_f32(float %a) nounwind { ; RV64IF-NEXT: fcvt.l.s a0, ft0 ; RV64IF-NEXT: ret ; +; RV32I-LABEL: llrint_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call llrintf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: llrint_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 @@ -948,6 +1205,15 @@ define i64 @llround_f32(float %a) nounwind { ; RV64IF-NEXT: fcvt.l.s a0, ft0, rmm ; RV64IF-NEXT: ret ; +; RV32I-LABEL: llround_f32: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call llroundf@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; ; RV64I-LABEL: llround_f32: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 -- 2.7.4