From 8812157b11eac4f8ed578bc9cad19cdd826b3339 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Tue, 10 Sep 2019 15:42:22 +0000
Subject: [PATCH] [x86] add a test for BreakFalseDeps; NFC

As discussed in D67363

llvm-svn: 371528
---
 llvm/test/CodeGen/X86/sqrt-partial.ll | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/llvm/test/CodeGen/X86/sqrt-partial.ll b/llvm/test/CodeGen/X86/sqrt-partial.ll
index 8f78795..d017b5c 100644
--- a/llvm/test/CodeGen/X86/sqrt-partial.ll
+++ b/llvm/test/CodeGen/X86/sqrt-partial.ll
@@ -85,6 +85,26 @@ define double @minsize(double %x, double %y) minsize {
   ret double %t6
 }
 
+; Partial reg avoidance may involve register allocation
+; rather than adding an instruction.
+
+define double @partial_dep_minsize(double %x, double %y) minsize {
+; SSE-LABEL: partial_dep_minsize:
+; SSE:       # %bb.0:
+; SSE-NEXT:    sqrtsd %xmm1, %xmm0
+; SSE-NEXT:    addsd %xmm1, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: partial_dep_minsize:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vsqrtsd %xmm1, %xmm1, %xmm0
+; AVX-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %t6 = tail call fast double @llvm.sqrt.f64(double %y)
+  %t = fadd fast double %t6, %y
+  ret double %t
+}
+
 declare float @sqrtf(float)
 declare double @sqrt(double)
 declare double @llvm.sqrt.f64(double)
-- 
2.7.4